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Searched refs:getInterval (Results 1 – 25 of 44) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp112 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn(); in processBlock()
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
196 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
213 !LIS->getInterval(AddendSrcReg).liveAt(FMAIdx)) in processBlock()
281 LiveInterval &FMAInt = LIS->getInterval(OldFMAReg); in processBlock()
299 LiveInterval &NewFMAInt = LIS->getInterval(KilledProdReg); in processBlock()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp46 LiveInterval &OldLI = LIS.getInterval(OldReg); in createEmptyIntervalFrom()
66 LIS.getInterval(VReg).markNotSpillable(); in createFrom()
85 LiveInterval &OrigLI = LIS.getInterval(Original); in scanRemattable()
122 LiveInterval &li = LIS.getInterval(MO.getReg()); in allUsesAvailableAt()
313 LiveInterval &OrigLI = LIS.getInterval(Original); in eliminateDeadDef()
338 LiveInterval &LI = LIS.getInterval(Reg); in eliminateDeadDef()
420 ToShrink.remove(&LIS.getInterval(Reg)); in eliminateDeadDef()
488 LiveInterval &LI = LIS.getInterval(get(I)); in calculateRegClassAndHint()
H A DInlineSpiller.cpp274 LIS.getInterval(MO.getReg()); in getVDefInterval()
342 LiveInterval &SnipLI = LIS.getInterval(SnipReg); in collectRegsToSpill()
386 LiveInterval &SrcLI = LIS.getInterval(SrcReg); in hoistSpillInsideBB()
397 LiveInterval &OrigLI = LIS.getInterval(Original); in hoistSpillInsideBB()
589 LiveInterval &OrigLI = LIS.getInterval(Original); in reMaterializeFor()
666 LiveInterval &LI = LIS.getInterval(Reg); in reMaterializeAll()
683 LiveInterval &LI = LIS.getInterval(Reg); in reMaterializeAll()
1060 LiveInterval &OldLI = LIS.getInterval(Reg); in spillAroundUses()
1161 StackInt = &LSS.getInterval(StackSlot); in spillAll()
1233 LiveInterval &OrigLI = LIS.getInterval(Original); in addToMergeableSpills()
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H A DSplitKit.cpp327 const LiveInterval &Orig = LIS.getInterval(OrigReg); in isOriginalEndpoint()
469 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defValue()
586 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defFromParent()
594 LiveInterval &OrigLI = LIS.getInterval(Original); in defFromParent()
843 LiveInterval *LI = &LIS.getInterval(Edit->get(0)); in removeBackCopies()
950 LiveInterval *LI = &LIS.getInterval(Edit->get(0)); in computeRedundantBackCopies()
1003 LiveInterval *LI = &LIS.getInterval(Edit->get(0)); in hoistCopies()
1419 LiveInterval &LI = LIS.getInterval(R); in rewriteAssigned()
1431 LiveInterval *LI = &LIS.getInterval(R); in deleteRematVictims()
1538 LiveInterval &LI = LIS.getInterval(Reg); in finish()
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H A DRegisterCoalescer.cpp1293 LiveInterval &SrcInt = LIS->getInterval(SrcReg); in reMaterializeTrivialDef()
1436 LiveInterval &DstInt = LIS->getInterval(DstReg); in reMaterializeTrivialDef()
1625 const LiveInterval &SrcLI = LIS->getInterval(SrcReg); in eliminateUndefCopy()
1640 LiveInterval &DstLI = LIS->getInterval(DstReg); in eliminateUndefCopy()
2135 dbgs() << LIS->getInterval(CP.getDstReg()); in joinCopy()
2148 LiveInterval &RHS = LIS->getInterval(SrcReg); in joinReservedPhysReg()
2591 const LiveInterval &LI = LIS->getInterval(SrcReg); in followCopyChain()
2871 auto &OtherLI = LIS->getInterval(Other.Reg); in analyzeValue()
3900 LiveInterval &LI = LIS->getInterval(reg); in lateLiveIntervalUpdate()
3982 if (LIS->getInterval(OtherReg).overlaps(DstLI)) { in applyTerminalRule()
[all …]
H A DRegAllocBase.cpp78 enqueue(&LIS->getInterval(Reg)); in seedLiveRegs()
149 LiveInterval *SplitVirtReg = &LIS->getInterval(Reg); in allocatePhysRegs()
H A DCalcSpillWeights.cpp41 calculateSpillWeightAndHint(LIS.getInterval(Reg)); in calculateSpillWeightsAndHints()
114 const LiveInterval &SrcLI = LIS.getInterval(Reg); in isRematerializable()
165 const LiveInterval &OrigInt = LIS.getInterval(Original); in weightCalcHelper()
H A DRegAllocPBQP.cpp201 LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight(); in apply()
334 LiveInterval &LI = LIS.getInterval(VReg); in apply()
607 LiveInterval &VRegLI = LIS.getInterval(VReg); in initializeGraph()
666 if (LIS.getInterval(VReg).empty()) { in initializeGraph()
695 LiveRangeEdit LRE(&LIS.getInterval(VReg), NewIntervals, MF, LIS, &VRM, in spillVReg()
707 const LiveInterval &LI = LIS.getInterval(R); in spillVReg()
762 LiveInterval &LI = LIS.getInterval(R); in finalizeAlloc()
H A DPHIElimination.cpp405 LiveInterval &DestLI = LIS->getInterval(DestReg); in LowerPHINode()
572 LiveInterval &SrcLI = LIS->getInterval(SrcReg); in LowerPHINode()
736 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB); in isLiveIn()
751 const LiveInterval &LI = LIS->getInterval(Reg); in isLiveOutPastPHIs()
H A DRegAllocBasic.cpp147 LiveInterval &LI = LIS->getInterval(VirtReg); in INITIALIZE_PASS_DEPENDENCY()
166 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
H A DTwoAddressInstructionPass.cpp299 LiveInterval &LI = LIS->getInterval(Reg); in isPlainlyKilled()
818 LiveInterval &LI = LIS->getInterval(Reg); in rescheduleMIBelowKill()
1008 LiveInterval &LI = LIS->getInterval(Reg); in rescheduleKillAboveMI()
1528 LiveInterval &LI = LIS->getInterval(RegA); in processTiedPairs()
1610 LiveInterval &LI = LIS->getInterval(RegB); in processTiedPairs()
1664 LiveInterval &LI = LIS->getInterval(RegB); in processStatepoint()
1665 for (auto &S : LIS->getInterval(RegA)) { in processStatepoint()
1809 LiveInterval &LI = LIS->getInterval(Reg); in runOnMachineFunction()
H A DRegAllocGreedy.cpp230 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_CanEraseVirtReg()
249 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
354 LiveInterval *LI = &LIS->getInterval(~CurQueue.top().second); in dequeue()
975 const LiveInterval &Reg = LIS->getInterval(LREdit.get(I)); in splitAroundRegion()
1200 const LiveInterval &LI = LIS->getInterval(LREdit.get(I)); in tryBlockSplit()
1594 ExtraInfo->setStage(LIS->getInterval(LREdit.get(I)), RS_Split2); in tryLocalSplit()
1875 if (RecoloringCandidates.count(&LIS->getInterval(R))) in tryLastChanceRecoloring()
2128 LiveInterval &LI = LIS->getInterval(Reg); in tryHintRecoloring()
H A DLiveIntervals.cpp160 OS << getInterval(Reg) << '\n'; in print()
389 const LiveInterval &LI = getInterval(Reg); in extendSegmentsToUses()
705 const LiveInterval &LI = getInterval(Reg); in addKillFlags()
1029 LiveInterval &LI = LIS.getInterval(Reg); in updateAllRanges()
1559 LiveInterval &LI = getInterval(Reg); in handleMoveIntoNewBundle()
1687 !getInterval(Reg).hasSubRanges() && in repairIntervalsInRange()
1703 LiveInterval &LI = getInterval(Reg); in repairIntervalsInRange()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp186 const LiveInterval &ld = LIs.getInterval(Rd); in addIntraChainConstraint()
187 const LiveInterval &la = LIs.getInterval(Ra); in addIntraChainConstraint()
262 const LiveInterval &ld = LIs.getInterval(Rd); in addInterChainConstraint()
268 const LiveInterval &lr = LIs.getInterval(r); in addInterChainConstraint()
321 const LiveInterval &LI = LIs.getInterval(reg); in regJustKilledBefore()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyOptimizeLiveIntervals.cpp96 LIS.splitSeparateComponents(LIS.getInterval(Reg), SplitLIs); in runOnMachineFunction()
116 LiveInterval &LI = LIS.getInterval(MI.getOperand(0).getReg()); in runOnMachineFunction()
H A DWebAssemblyMemIntrinsicResults.cpp91 LiveInterval *FromLI = &LIS.getInterval(FromReg); in replaceDominatedUses()
92 LiveInterval *ToLI = &LIS.getInterval(ToReg); in replaceDominatedUses()
H A DWebAssemblyRegStackify.cpp273 if (const VNInfo *ValNo = LIS.getInterval(Reg).getVNInfoBefore( in getVRegDef()
290 const LiveInterval &LI = LIS.getInterval(Reg); in hasOneUse()
435 const LiveInterval &LI = LIS.getInterval(Reg); in oneUseDominatesOtherUses()
543 LiveInterval &LI = LIS.getInterval(Reg); in moveForSingleUse()
585 LiveInterval &LI = LIS.getInterval(Reg); in rematerializeCheapDef()
658 LiveInterval &LI = LIS.getInterval(Reg); in moveAndTeeForMultiUse()
H A DWebAssemblyRegColoring.cpp108 LiveInterval *LI = &Liveness->getInterval(VReg); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DLiveStacks.h68 LiveInterval &getInterval(int Slot) { in getInterval() function
75 const LiveInterval &getInterval(int Slot) const { in getInterval() function
H A DLiveIntervals.h112 LiveInterval &getInterval(Register Reg) { in getInterval() function
119 const LiveInterval &getInterval(Register Reg) const { in getInterval() function
120 return const_cast<LiveIntervals*>(this)->getInterval(Reg); in getInterval()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp382 return !any_of(LIS.getInterval(DstReg), HasCall) && in shouldCoalesce()
383 !any_of(LIS.getInterval(SrcReg), HasCall); in shouldCoalesce()
391 return any_of(LIS.getInterval(LargeReg), HasCall) || in shouldCoalesce()
392 !any_of(LIS.getInterval(SmallReg), HasCall); in shouldCoalesce()
H A DHexagonExpandCondsets.cpp335 LiveInterval &LI = LIS->getInterval(Reg); in updateKillFlags()
427 LiveInterval &LI = LIS->getInterval(Reg); in updateDeadsInRange()
529 LiveInterval &LI = LIS->getInterval(Reg); in updateDeadFlags()
574 LIS->getInterval(R).verify(); in updateLiveness()
1134 LiveInterval &L1 = LIS->getInterval(R1.Reg); in coalesceRegisters()
1135 LiveInterval &L2 = LIS->getInterval(R2.Reg); in coalesceRegisters()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMaskingPreRA.cpp97 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx); in isDefBetween()
190 LiveInterval *SelLI = &LIS->getInterval(SelReg); in optimizeVcndVcmpPair()
241 LiveInterval &CCLI = LIS->getInterval(CCReg); in optimizeVcndVcmpPair()
267 LiveInterval *CmpLI = CmpReg.isVirtual() ? &LIS->getInterval(CmpReg) : nullptr; in optimizeVcndVcmpPair()
H A DGCNRegPressure.cpp33 const auto &LI = LIS.getInterval(Reg); in printLivesAt()
249 const auto &LI = LIS.getInterval(Reg); in getLiveLaneMask()
367 const LiveInterval &LI = LIS.getInterval(It.first); in advanceBeforeNext()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TileConfig.cpp192 LIS.extendToIndices(LIS.getInterval(R), {SIdx.getRegSlot()}); in INITIALIZE_PASS_DEPENDENCY()

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