Home
last modified time | relevance | path

Searched refs:getInstr (Results 1 – 25 of 102) sorted by relevance

12345

/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/
H A DSnippetGeneratorTest.cpp46 const Instruction &Instr = State.getIC().getInstr(Opcode); in checkAndGetCodeTemplates()
148 const Instruction &Instr = State.getIC().getInstr(Opcode); in TEST_F()
205 const Instruction &Instr = State.getIC().getInstr(Opcode); in TEST_F()
336 const Instruction &Instr = State.getIC().getInstr(Opcode); in TEST_F()
351 const Instruction &Instr = State.getIC().getInstr(Opcode); in TEST_F()
373 const Instruction &getInstr(unsigned Opcode) { in getInstr() function in llvm::exegesis::__anon52bcd7af0111::X86FakeSnippetGenerator
374 return State.getIC().getInstr(Opcode); in getInstr()
378 return {&getInstr(Opcode)}; in getInstructionTemplate()
444 Mov.getValueFor(Mov.getInstr().Variables[0]) = in TEST_F()
451 Add.getValueFor(Add.getInstr().Variables[0]) = in TEST_F()
[all …]
H A DTargetTest.cpp122 const Instruction &getInstr(unsigned OpCode) { in getInstr() function in llvm::exegesis::__anonc023aeec0111::X86TargetTest
123 return State.getIC().getInstr(OpCode); in getInstr()
362 const Instruction &I = getInstr(X86::ADD64rm); in TEST_F()
375 const Instruction &I = getInstr(X86::VGATHERDPSZ128rm); in TEST_F()
389 State.getExegesisTarget().allowAsBackToBack(getInstr(X86::ADD64rr))); in TEST_F()
391 State.getExegesisTarget().allowAsBackToBack(getInstr(X86::LEA64r))); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp31 if (QII->mayBeCurLoad(*SUd->getInstr())) in hasDependence()
34 if (QII->canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr())) in hasDependence()
57 if (SU->isInstr() && QII.mayBeCurLoad(*SU->getInstr())) { in SchedulingCost()
H A DHexagonSubtarget.cpp280 MachineInstr &MI1 = *SU.getInstr(); in apply()
341 if (DAG->SUnits[su].getInstr()->isCall()) in apply()
406 MachineInstr &L0 = *S0.getInstr(); in apply()
419 MachineInstr &L1 = *S1.getInstr(); in apply()
458 MachineInstr *SrcInst = Src->getInstr(); in adjustSchedDependency()
459 MachineInstr *DstInst = Dst->getInstr(); in adjustSchedDependency()
571 MachineInstr *SrcI = Src->getInstr(); in restoreLatency()
592 MachineInstr *DstI = Dst->getInstr(); in restoreLatency()
638 !I.getSUnit()->getInstr()->isPseudo()) in getZeroLatency()
650 MachineInstr &SrcInst = *Src->getInstr(); in isBestZeroLatency()
[all …]
H A DHexagonHazardRecognizer.cpp40 MachineInstr *MI = SU->getInstr(); in getHazardType()
98 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad()) in ShouldPreferAnother()
113 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
165 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
166 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
H A DHexagonVLIWPacketizer.cpp422 if (PacketSU->getInstr()->isInlineAsm()) in canPromoteToDotCur()
516 assert(SUI->getInstr() && SUJ->getInstr()); in updateOffset()
517 MachineInstr &MI = *SUI->getInstr(); in updateOffset()
518 MachineInstr &MJ = *SUJ->getInstr(); in updateOffset()
673 if (PacketSU->getInstr()->mayStore()) in canPromoteToNewValueStore()
1325 assert(SUI->getInstr() && SUJ->getInstr()); in isLegalToPacketizeTogether()
1326 MachineInstr &I = *SUI->getInstr(); in isLegalToPacketizeTogether()
1327 MachineInstr &J = *SUJ->getInstr(); in isLegalToPacketizeTogether()
1643 assert(SUI->getInstr() && SUJ->getInstr()); in isLegalToPruneDependencies()
1644 MachineInstr &I = *SUI->getInstr(); in isLegalToPruneDependencies()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/AsmPrinter/
H A DDebugHandlerBase.cpp300 Entries.front().getInstr()->getDebugVariable(); in beginFunction()
303 if (!IsDescribedByReg(Entries.front().getInstr())) in beginFunction()
304 LabelsBeforeInsn[Entries.front().getInstr()] = Asm->getFunctionBegin(); in beginFunction()
305 if (Entries.front().getInstr()->getDebugExpression()->isFragment()) { in beginFunction()
310 const DIExpression *Fragment = I->getInstr()->getDebugExpression(); in beginFunction()
315 Pred.getInstr()->getDebugExpression()); in beginFunction()
322 if (IsDescribedByReg(I->getInstr())) in beginFunction()
324 LabelsBeforeInsn[I->getInstr()] = Asm->getFunctionBegin(); in beginFunction()
331 requestLabelBeforeInsn(Entry.getInstr()); in beginFunction()
333 requestLabelAfterInsn(Entry.getInstr()); in beginFunction()
H A DDbgEntityHistoryCalculator.cpp79 Entries.back().getInstr()->isIdenticalTo(MI)) { in startDbgValue()
81 << "\t" << Entries.back().getInstr() << "\t" << MI in startDbgValue()
95 if (Entries.back().isClobber() && Entries.back().getInstr() == &MI) in startClobber()
197 const MachineInstr *StartMI = EI->getInstr(); in trimLocationRanges()
264 const MachineInstr *MI = Entry.getInstr(); in hasNonEmptyLocation()
338 if (Entry.getInstr()->isDebugEntryValue()) in clobberRegEntries()
340 if (Entry.getInstr()->hasDebugOperandForReg(RegNo)) { in clobberRegEntries()
343 for (const auto &MO : Entry.getInstr()->debug_operands()) in clobberRegEntries()
347 for (const auto &MO : Entry.getInstr()->debug_operands()) in clobberRegEntries()
378 const MachineInstr &DV = *Entry.getInstr(); in handleNewDebugValue()
[all …]
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DSnippetGenerator.cpp48 if (Variant.getInstr().hasMemoryOperands()) { in generateConfigurations()
59 for (const auto &Op : Variant.getInstr().Operands) { in generateConfigurations()
121 for (const Operand &Op : IT.getInstr().Operands) { in computeRegisterInitialValues()
131 for (const Operand &Op : IT.getInstr().Operands) { in computeRegisterInitialValues()
144 const AliasingConfigurations SelfAliasing(Variant.getInstr(), in generateSelfAliasingCodeTemplates()
145 Variant.getInstr()); in generateSelfAliasingCodeTemplates()
264 for (const Variable &Var : IT.getInstr().Variables) { in randomizeUnsetVariables()
267 if (auto Err = randomizeMCOperand(State, IT.getInstr(), Var, in randomizeUnsetVariables()
H A DSerialSnippetGenerator.cpp51 const Instruction &OtherInstr = State.getIC().getInstr(OtherOpcode); in computeAliasingInstructions()
118 const AliasingConfigurations SelfAliasing(Variant.getInstr(), in appendCodeTemplates()
119 Variant.getInstr()); in appendCodeTemplates()
133 const Instruction &Instr = Variant.getInstr(); in appendCodeTemplates()
166 getExecutionModes(Variant.getInstr(), ForbiddenRegisters); in generateCodeTemplates()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp154 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
155 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
188 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
213 MachineInstr *MI = SU->getInstr(); in getAluKind()
287 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
316 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
318 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { in PopInst()
387 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
436 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
H A DAMDGPUIGroupLP.cpp87 << "from: SU(" << A->NodeNum << ") " << *A->getInstr() in tryAddEdge()
88 << "to: SU(" << B->NodeNum << ") " << *B->getInstr()); in tryAddEdge()
134 MachineInstr &MI = *SU.getInstr(); in canAddSU()
304 if (SU.getInstr()->getOpcode() == AMDGPU::SCHED_BARRIER) in apply()
309 MachineInstr &MI = *SchedBarrier.getInstr(); in addSchedBarrierEdges()
414 assert(SU.getInstr()->getOpcode() == AMDGPU::SCHED_BARRIER); in resetSchedBarrierEdges()
H A DGCNDPPCombine.cpp231 if (TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, SDst)) { in createDPPInst()
277 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) { in createDPPInst()
301 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) { in createDPPInst()
320 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) || in createDPPInst()
321 !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) { in createDPPInst()
390 DPPInst.getInstr()->eraseFromParent(); in createDPPInst()
393 LLVM_DEBUG(dbgs() << " combined: " << *DPPInst.getInstr()); in createDPPInst()
394 return DPPInst.getInstr(); in createDPPInst()
584 DPPMIs.push_back(UndefInst.getInstr()); in combineDPPMov()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMacroFusion.cpp93 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " in fuseInstructionPair()
94 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); in fuseInstructionPair()
160 if (DAG->ExitSU.getInstr()) in apply()
168 const MachineInstr &AnchorMI = *AnchorSU.getInstr(); in scheduleAdjacentImpl()
187 const MachineInstr *DepMI = DepSU.getInstr(); in scheduleAdjacentImpl()
H A DMachinePipeliner.cpp618 Cycles[SU->getInstr()] = Cycle; in schedule()
846 MachineInstr *MI = I.getInstr(); in updatePhiDependences()
904 if (I.getInstr()->isPHI()) { in updatePhiDependences()
1362 if (!SU.getInstr()->isCopy() && !SU.getInstr()->isRegSequence()) in apply()
2042 SU->getInstr()->dump(); in schedulePipeline()
2391 SU->getInstr()->dump(); in insert()
2404 SU->getInstr()->dump(); in insert()
2673 if (UseSU->getInstr()->isPHI()) in isLoopCarried()
2727 if (SU->getInstr()->isPHI()) in computeUnpipelineableNodes()
2977 if (SU->getInstr()->isPHI()) in finalizeSchedule()
[all …]
H A DScheduleDAGInstrs.cpp260 RegUse = UseSU->getInstr(); in addPhysRegDataDeps()
283 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
387 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
435 MachineInstr *Use = UseSU->getInstr(); in addVRegDefDeps()
506 const MachineInstr *MI = SU->getInstr(); in addVRegUseDeps()
540 if (SUa->getInstr()->mayAlias(AAForDep, *SUb->getInstr(), UseTBAA)) { in addChainDependency()
1158 SU.getInstr()->dump(); in dumpNode()
1164 if (EntrySU.getInstr() != nullptr) in dump()
1168 if (ExitSU.getInstr() != nullptr) in dump()
1181 SU->getInstr()->print(oss, /*IsStandalone=*/true); in getGraphNodeLabel()
[all …]
H A DVLIWMachineScheduler.cpp109 if (!SU || !SU->getInstr()) in isResourceAvailable()
114 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
116 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
162 switch (SU->getInstr()->getOpcode()) { in reserveResources()
164 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
186 LLVM_DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
326 assert(SU->getInstr() && "Scheduled SUnit must have instr"); in releaseBottomNode()
365 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard()
432 IssueCount += SchedModel->getNumMicroOps(SU->getInstr()); in bumpNode()
532 TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta, in readyQueueVerboseDump()
[all …]
H A DSlotIndexes.cpp125 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeMachineInstrFromMaps()
138 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeSingleMachineInstrFromMaps()
208 MachineInstr *SlotMI = ListI->getInstr(); in repairIndexesInRange()
245 if (ILE.getInstr()) { in dump()
246 dbgs() << *ILE.getInstr(); in dump()
H A DMachineScheduler.cpp800 MachineInstr *MI = SU->getInstr(); in schedule()
948 const MachineInstr &MI = *SU.getInstr(); in collectVRegUses()
1184 if (EntrySU.getInstr() != nullptr) in dump()
1200 if (ExitSU.getInstr() != nullptr) in dump()
1407 MachineInstr *MI = SU->getInstr(); in scheduleMI()
1955 if (!SU.getInstr()->isCopy()) in apply()
3143 Cand.SU->getInstr(), in initCandidate()
3150 Cand.SU->getInstr(), in initCandidate()
3157 Cand.SU->getInstr(), in initCandidate()
3437 << *SU->getInstr()); in pickNode()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
169 OS << TII->getName(SU->getInstr()->getOpcode()); in dumpSU()
204 if (has4RegOps(SU->getInstr())) in dumpSU()
285 LastEmittedMI = SU->getInstr(); in EmitInstruction()
291 LastEmittedMI = SU->getInstr(); in EmitInstruction()
329 CurrGroupHas4RegOps |= has4RegOps(SU->getInstr()); in EmitInstruction()
364 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in groupingCost()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/PowerPC/
H A DTarget.cpp19 const auto Op = IT.getInstr().Operands[OpIdx]; in setMemOp()
77 if (IT.getInstr().hasTiedRegisters()) in fillMemoryOperands()
80 const auto DispOp = IT.getInstr().Operands[DispOpIdx]; in fillMemoryOperands()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp374 LLVM_DEBUG(dbgs() << "Remove " << *MIB.getInstr() << '\n'); in ExpandMOVX_RR()
377 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to MOV\n"); in ExpandMOVX_RR()
389 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to "); in ExpandMOVSZX_RR()
420 BuildMI(MBB, MIB.getInstr(), DL, get(Move), Dst).addReg(SSrc); in ExpandMOVSZX_RR()
425 AddSExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst); in ExpandMOVSZX_RR()
428 AddZExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst); in ExpandMOVSZX_RR()
439 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to LOAD and "); in ExpandMOVSZX_RM()
457 MachineBasicBlock::iterator I = MIB.getInstr(); in ExpandMOVSZX_RM()
475 MachineBasicBlock::iterator I = MIB.getInstr(); in ExpandPUSH_POP()
511 auto MI = MIB.getInstr(); in ExpandMOVEM()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCMachineScheduler.cpp25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI || in isADDIInstr()
26 Cand.SU->getInstr()->getOpcode() == PPC::ADDI8; in isADDIInstr()
37 if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) { in biasAddiLoadCandidate()
41 if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) { in biasAddiLoadCandidate()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp47 MachineInstr *MI = SU->getInstr(); in getHazardType()
90 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
185 MachineInstr &L0 = *SU->getInstr(); in getHazardType()
257 MachineInstr &MI = *SU->getInstr(); in EmitInstruction()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64MachineScheduler.cpp66 MachineInstr *Instr0 = TryCand.SU->getInstr(); in tryCandidate()
67 MachineInstr *Instr1 = Cand.SU->getInstr(); in tryCandidate()

12345