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Searched refs:getImm (Results 1 – 25 of 438) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ClauseMergePass.cpp80 .getImm(); in getCFAluSize()
87 .getImm(); in isCFAluEnabled()
128 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
129 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
130 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
144 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
145 RootCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
153 if (LatrCFAlu.getOperand(Mode0Idx).getImm()) { in mergeIfPossible()
155 LatrCFAlu.getOperand(Mode0Idx).getImm()); in mergeIfPossible()
161 if (LatrCFAlu.getOperand(Mode1Idx).getImm()) { in mergeIfPossible()
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H A DGCNDPPCombine.cpp212 RowMaskOpnd->getImm() == 0xF && BankMaskOpnd->getImm() == 0xF; in createDPPInst()
268 DPPInst.addImm(Mod0->getImm()); in createDPPInst()
292 DPPInst.addImm(Mod1->getImm()); in createDPPInst()
315 DPPInst.addImm(Mod2->getImm()); in createDPPInst()
349 auto OpSel = OpSelOpr->getImm(); in createDPPInst()
375 DPPInst.addImm(NegOpr->getImm()); in createDPPInst()
415 if (OldOpnd->getImm() == 0) in isIdentityValue()
442 if (OldOpnd->getImm() == 1) in isIdentityValue()
483 return (Imm->getImm() & Mask) == Value; in hasNoImmOrEqual()
526 bool BoundCtrlZero = BCZOpnd->getImm(); in combineDPPMov()
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/llvm-project-15.0.7/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVInstPrinter.cpp53 uint64_t Imm = MI->getOperand(StartIndex).getImm(); in printOpConstantVarOps()
54 Imm |= (MI->getOperand(StartIndex + 1).getImm() << 32); in printOpConstantVarOps()
153 if (MI->getOperand(i).getImm() & in printInst()
201 auto Dec = static_cast<SPIRV::Decoration>(DecOp.getImm()); in printOpDecorate()
256 O << formatImm((int64_t)Op.getImm()); in printOperand()
290 MI->getOperand(1).getImm() == in printStringImm()
308 static_cast<SPIRV::Capability>(MI->getOperand(OpNo).getImm()); in printCapability()
380 MI->getOperand(OpNo).getImm()); in printSamplerAddressingMode()
425 unsigned e = static_cast<unsigned>(MI->getOperand(OpNo).getImm()); in printImageOperand()
471 MI->getOperand(OpNo).getImm()); in printFunctionParameterAttribute()
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/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZTargetStreamer.h31 A.getNumOperands() == 5 && A.getOperand(2).getImm() == 1 && in operator()
32 B.getOperand(2).getImm() == 1 && "Unexpected EXRL target MCInst"); in operator()
37 if (A.getOperand(1).getImm() != B.getOperand(1).getImm()) in operator()
38 return A.getOperand(1).getImm() < B.getOperand(1).getImm(); in operator()
41 if (A.getOperand(4).getImm() != B.getOperand(4).getImm()) in operator()
42 return A.getOperand(4).getImm() < B.getOperand(4).getImm(); in operator()
H A DSystemZAsmPrinter.cpp37 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
42 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
51 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
56 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
66 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
67 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
68 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
118 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
128 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
166 .addImm(MI->getOperand(0).getImm()) in emitInstruction()
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/llvm-project-15.0.7/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp79 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
85 MI->getOperand(OpNum + 1).getImm() == 0 && in printMemASXOperand()
88 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
96 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASXOperand()
123 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASOperandASX()
130 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASOperandASX()
154 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASOperandRRM()
161 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASOperandRRM()
185 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASOperandHM()
208 int CC = (int)MI->getOperand(OpNum).getImm(); in printCCOperand()
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/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp598 unsigned Imm = MO.getImm(); in printPostIdxImm8Operand()
609 O << (MO2.getImm() ? "" : "-"); in printPostIdxRegOperand()
617 unsigned Imm = MO.getImm(); in printPostIdxImm8s4Operand()
708 if (MO2.getImm()) { in printAddrMode6Operand()
709 O << ":" << (MO2.getImm() << 3); in printAddrMode6Operand()
741 uint32_t v = ~MO.getImm(); in printBitfieldInvMaskImmOperand()
838 if (Op.getImm()) in printSetendOperand()
853 unsigned IFlags = Op.getImm(); in printCPSIFlag()
907 unsigned Mask = Op.getImm() & 0xf; in printMSRMaskOperand()
1266 if (MO2.getImm()) { in printT2AddrModeImm0_1020s4Operand()
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H A DARMMCCodeEmitter.cpp329 return MO.getImm(); in getModImmOpValue()
762 return MO.getImm() >> 2; in getARMBranchTargetOpValue()
777 return MO.getImm() >> 2; in getARMBLTargetOpValue()
918 return MO.getImm(); in getThumbAdrLabelOpValue()
1604 Value |= MO3.getImm(); in getT2AddrModeSORegOpValue()
1766 switch (Imm.getImm()) { in getAddrMode6AddressOpValue()
1790 switch (Imm.getImm()) { in getAddrMode6OneLane32AddressOpValue()
1817 switch (Imm.getImm()) { in getAddrMode6DupAddressOpValue()
1900 return isNeg ? -(MO.getImm() >> 1) : (MO.getImm() >> 1); in getBFTargetOpValue()
1920 int Diff = MO.getImm() - BranchMO.getImm(); in getBFAfterTargetOpValue()
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H A DARMMCTargetDesc.cpp43 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo()
426 int64_t Imm = Inst.getOperand(OpNum).getImm(); in evaluateBranch()
454 int32_t OffImm = (int32_t)MO2.getImm(); in evaluateMemOpAddrForAddrMode_i12()
474 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()); in evaluateMemOpAddrForAddrMode3()
475 ARM_AM::AddrOpc Op = ARM_AM::getAM3Op(MO3.getImm()); in evaluateMemOpAddrForAddrMode3()
494 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm()); in evaluateMemOpAddrForAddrMode5()
495 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm()); in evaluateMemOpAddrForAddrMode5()
513 unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm()); in evaluateMemOpAddrForAddrMode5FP16()
514 ARM_AM::AddrOpc Op = ARM_AM::getAM5FP16Op(MO2.getImm()); in evaluateMemOpAddrForAddrMode5FP16()
533 int32_t OffImm = (int32_t)MO2.getImm(); in evaluateMemOpAddrForAddrModeT2_i8s4()
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/llvm-project-15.0.7/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp138 unsigned AluCode = AluOp.getImm(); in adjustPqBits()
201 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
204 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
205 if (Op2.getImm() != 0) { in getRiMemoryOpValue()
206 if (LPAC::isPreOp(AluOp.getImm())) in getRiMemoryOpValue()
208 if (LPAC::isPostOp(AluOp.getImm())) in getRiMemoryOpValue()
232 unsigned AluOp = AluMCOp.getImm(); in getRrMemoryOpValue()
272 assert(isInt<10>(Op2.getImm()) && in getSplsOpValue()
275 Encoding |= (Op2.getImm() & 0x3ff); in getSplsOpValue()
276 if (Op2.getImm() != 0) { in getSplsOpValue()
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H A DLanaiInstPrinter.cpp49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
61 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
66 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
156 OS << formatHex(Op.getImm()); in printOperand()
181 OS << formatHex(Op.getImm() << 16); in printHi16ImmOperand()
205 OS << formatHex(0xffff0000 | Op.getImm()); in printLo16AndImmOperand()
232 OS << OffsetOp.getImm(); in printMemoryImmediateOffset()
243 const unsigned AluCode = AluOp.getImm(); in printMemRiOperand()
258 const unsigned AluCode = AluOp.getImm(); in printMemRrOperand()
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp247 int64_t getImm() const { in getImm() function
354 return (Kind == Immediate && getImm() <= -8 && getImm() >= -512 && in isHashImmX8()
355 (getImm() & 7) == 0); in isHashImmX8()
360 (Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0); in isS34ImmX16()
375 if ((getImm() & 3) != 0) in isDirectBr()
377 if (isInt<26>(getImm())) in isDirectBr()
381 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm()))) in isDirectBr()
395 return Kind == Immediate && isUInt<6>(getImm()) && ((getImm() & 1) == 0); in isVSRpEvenRegNumber()
711 OS << getImm(); in print()
854 int64_t N = Inst.getOperand(2).getImm(); in ProcessInstruction()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp73 int64_t Imm = MI->getOperand(OpNo).getImm(); in printU16ImmOperand()
103 if (MI->getOperand(OpNo).getImm()) { in printNamedBit()
159 if (MI->getOperand(OpNo).getImm()) { in printOffset0()
168 if (MI->getOperand(OpNo).getImm()) { in printOffset1()
206 auto Imm = MI->getOperand(OpNo).getImm(); in printCPol()
232 if (MI->getOperand(OpNo).getImm()) { in printDMask()
707 if (!isUInt<16>(Op.getImm()) && in printRegularOperand()
729 O << formatDec(Op.getImm()); in printRegularOperand()
1087 if (MI->getOperand(ComprIdx).getImm()) in printExpSrcN()
1303 if (Op.getImm() == 1) { in printIfSet()
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H A DR600InstPrinter.cpp36 int BankSwizzle = MI->getOperand(OpNo).getImm(); in printBankSwizzle()
64 unsigned CT = MI->getOperand(OpNo).getImm(); in printCT()
79 int KCacheMode = MI->getOperand(OpNo).getImm(); in printKCache()
81 int KCacheBank = MI->getOperand(OpNo - 2).getImm(); in printKCache()
83 int KCacheAddr = MI->getOperand(OpNo + 2).getImm(); in printKCache()
99 int64_t Imm = Op.getImm(); in printLiteral()
114 switch (MI->getOperand(OpNo).getImm()) { in printOMOD()
155 O << Op.getImm(); in printOperand()
178 unsigned Sel = MI->getOperand(OpNo).getImm(); in printRSel()
219 if (Op.getImm() == 0) { in printWrite()
H A DR600MCCodeEmitter.cpp99 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset in encodeInstruction()
108 int64_t Sampler = MI.getOperand(14).getImm(); in encodeInstruction()
111 MI.getOperand(2).getImm(), in encodeInstruction()
112 MI.getOperand(3).getImm(), in encodeInstruction()
113 MI.getOperand(4).getImm(), in encodeInstruction()
114 MI.getOperand(5).getImm() in encodeInstruction()
117 MI.getOperand(6).getImm() & 0x1F, in encodeInstruction()
118 MI.getOperand(7).getImm() & 0x1F, in encodeInstruction()
119 MI.getOperand(8).getImm() & 0x1F in encodeInstruction()
179 return MO.getImm(); in getMachineOpValue()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp240 return MO.getImm(); in getAdrLabelOpValue()
302 return MO.getImm(); in getCondBranchTargetOpValue()
324 return MO.getImm(); in getLoadLiteralOpValue()
352 return MO.getImm(); in getMoveWideImmOpValue()
372 return MO.getImm(); in getTestBranchTargetOpValue()
394 return MO.getImm(); in getBranchTargetOpValue()
421 switch (MO.getImm()) { in getVecShifterOpValue()
444 return 64 - MO.getImm(); in getFixedPointScaleOpValue()
480 return 8 - MO.getImm(); in getVecShiftR8OpValue()
516 return MO.getImm() - 8; in getVecShiftL8OpValue()
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H A DAArch64InstPrinter.cpp93 switch (Op3.getImm()) { in printInst()
129 int64_t immr = Op2.getImm(); in printInst()
130 int64_t imms = Op3.getImm(); in printInst()
160 if (Op2.getImm() > Op3.getImm()) { in printInst()
163 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
171 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
783 unsigned Op1Val = Op1.getImm(); in printSysAlias()
784 unsigned CnVal = Cn.getImm(); in printSysAlias()
785 unsigned CmVal = Cm.getImm(); in printSysAlias()
941 unsigned svcrop = MO.getImm(); in printSVCROp()
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCInstPrinter.cpp115 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
116 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
117 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
139 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
189 unsigned char L = MI->getOperand(0).getImm(); in printInst()
222 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
319 unsigned Code = MI->getOperand(OpNo).getImm(); in printATBitsAsHint()
361 int Value = MI->getOperand(OpNo).getImm(); in printS5ImmOperand()
428 O << (short)MI->getOperand(OpNo).getImm(); in printS16ImmOperand()
523 O << MI->getOperand(OpNo).getImm(); in printMemRegImmHash()
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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DStackMaps.h47 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); } in getID()
51 return MI->getOperand(NBytesPos).getImm(); in getNumPatchBytes()
101 uint64_t getID() const { return getMetaOper(IDPos).getImm(); } in getID()
105 return getMetaOper(NBytesPos).getImm(); in getNumPatchBytes()
115 return getMetaOper(CCPos).getImm(); in getCallingConv()
122 return MI->getOperand(getMetaIdx(NArgPos)).getImm(); in getNumCallArgs()
204 uint64_t getID() const { return MI->getOperand(NumDefs + IDPos).getImm(); } in getID()
208 return MI->getOperand(NumDefs + NBytesPos).getImm(); in getNumPatchBytes()
218 return MI->getOperand(getCCIdx()).getImm(); in getCallingConv()
222 uint64_t getFlags() const { return MI->getOperand(getFlagsIdx()).getImm(); } in getFlags()
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/llvm-project-15.0.7/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp161 const MCExpr *getImm() const { in getImm() function
409 addExpr(Inst, getImm()); in addImmOperands()
414 addExpr(Inst, getImm()); in addBrTargetOperands()
419 addExpr(Inst, getImm()); in addCallTargetOperands()
424 addExpr(Inst, getImm()); in addCondCodeOperands()
458 addExpr(Inst, getImm()); in addImmShiftOperands()
463 addExpr(Inst, getImm()); in addImm10Operands()
471 else if (isa<LanaiMCExpr>(getImm())) { in addLoImm16Operands()
563 OS << "Imm: " << getImm() << "\n"; in print()
614 const MCExpr *Imm = Op->getImm(); in MorphToMemImm()
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/llvm-project-15.0.7/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp35 return MO.getImm() - 1; in getOImmOpValue()
45 auto V = (MO.getImm() <= 3) ? 4 : MO.getImm(); in getImmOpValueIDLY()
57 return MSB.getImm() - LSB.getImm(); in getImmOpValueMSBSize()
135 .addImm(MI.getOperand(2).getImm() + 1); in expandRSUBI()
225 auto V = 1 << MI.getOperand(1).getImm(); in encodeInstruction()
252 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
266 unsigned Rz = MI.getOperand(Idx + 1).getImm(); in getRegSeqImmOpValue()
291 if (MI.getOperand(Idx).getImm() == 16) in getImmJMPIX()
293 else if (MI.getOperand(Idx).getImm() == 24) in getImmJMPIX()
295 else if (MI.getOperand(Idx).getImm() == 32) in getImmJMPIX()
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H A DCSKYInstPrinter.cpp136 O << formatHex(MO.getImm()); in printOperand()
138 O << MO.getImm(); in printOperand()
153 O << MO.getImm(); in printDataSymbol()
166 uint64_t Target = Address + MO.getImm(); in printConstpool()
170 O << MO.getImm(); in printConstpool()
192 uint64_t Target = Address + MO.getImm(); in printCSKYSymbolOperand()
196 O << MO.getImm(); in printCSKYSymbolOperand()
202 auto V = MI->getOperand(OpNo).getImm(); in printPSRFlag()
227 auto V = MI->getOperand(OpNum).getImm(); in printRegisterList()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCCodeEmitter.cpp100 encodeSLEB128(int32_t(MO.getImm()), OS); in encodeInstruction()
103 encodeULEB128(uint32_t(MO.getImm()), OS); in encodeInstruction()
106 encodeSLEB128(int64_t(MO.getImm()), OS); in encodeInstruction()
110 support::endian::write<uint8_t>(OS, MO.getImm(), support::little); in encodeInstruction()
113 support::endian::write<uint16_t>(OS, MO.getImm(), support::little); in encodeInstruction()
116 support::endian::write<uint32_t>(OS, MO.getImm(), support::little); in encodeInstruction()
119 support::endian::write<uint64_t>(OS, MO.getImm(), support::little); in encodeInstruction()
124 encodeULEB128(uint64_t(MO.getImm()), OS); in encodeInstruction()
127 encodeULEB128(uint64_t(MO.getImm()), OS); in encodeInstruction()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp636 O << MO.getImm(); in printOperand()
708 if (MO.isImm() && MO.getImm() == 0) { in PrintAsmOperand()
1257 MI->getOperand(1).getImm() == 0) { in emitInstruction()
1463 assert(MI->getOperand(0).getImm() < 0 && in emitInstruction()
1474 assert(MI->getOperand(1).getImm() < 0 && in emitInstruction()
1481 if (MI->getOperand(1).getImm() == 30 && MI->getOperand(0).getImm() >= 19 && in emitInstruction()
1482 MI->getOperand(0).getImm() <= 28) { in emitInstruction()
1489 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) && in emitInstruction()
1496 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) && in emitInstruction()
1517 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) && in emitInstruction()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp652 int64_t V = HiOperand.getImm(); in emitConst64()
675 .addImm(HiOperand.getImm()) in emitCombineII()
691 .addImm(HiOperand.getImm()) in emitCombineII()
706 .addImm(HiOperand.getImm()) in emitCombineII()
721 .addImm(HiOperand.getImm()) in emitCombineII()
732 .addImm(HiOperand.getImm()) in emitCombineII()
740 .addImm(HiOperand.getImm()) in emitCombineII()
748 .addImm(HiOperand.getImm()) in emitCombineII()
749 .addImm(LoOperand.getImm()); in emitCombineII()
796 .addImm(HiOperand.getImm()) in emitCombineIR()
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