[PowerPC] Support ppc-asm-full-reg-names for AIX

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D94282

[PowerPC] Emit dcbt and dcbtst in place of their extended mnemonics on AIX

On AIX, the system assembler does not support the extended mnemonics
dcbtt and dcbtstt. This patch stops them from being em

[PowerPC] Emit dcbt and dcbtst in place of their extended mnemonics on AIX

On AIX, the system assembler does not support the extended mnemonics
dcbtt and dcbtstt. This patch stops them from being emitted on
AIX and emits the base mnemonics instead, dcbt X, X, 16 and
dcbtstt X, X, 16 respectively.

Differential revision: https://reviews.llvm.org/D111258

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[PowerPC] Add ROP Protection Instructions for PowerPC

There are four new PowerPC instructions that are introduced in
Power 10. They are hashst, hashchk, hashstp, hashchkp.

These instructions will b

[PowerPC] Add ROP Protection Instructions for PowerPC

There are four new PowerPC instructions that are introduced in
Power 10. They are hashst, hashchk, hashstp, hashchkp.

These instructions will be used for ROP Protection.
This patch adds the four instructions.

Reviewed By: nemanjai, amyk, #powerpc

Differential Revision: https://reviews.llvm.org/D99375

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Revert "[PowerPC] Add ROP Protection Instructions for PowerPC"

This reverts commit 16fe741c69429235210c03c46420f8fa6aece4a1.

Reason: Broke the UBSan buildbots. More information available in the
pha

Revert "[PowerPC] Add ROP Protection Instructions for PowerPC"

This reverts commit 16fe741c69429235210c03c46420f8fa6aece4a1.

Reason: Broke the UBSan buildbots. More information available in the
phabricator review: https://reviews.llvm.org/D99375

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[PowerPC] Add ROP Protection Instructions for PowerPC

There are four new PowerPC instructions that are introduced in
Power 10. They are hashst, hashchk, hashstp, hashchkp.

These instructions will b

[PowerPC] Add ROP Protection Instructions for PowerPC

There are four new PowerPC instructions that are introduced in
Power 10. They are hashst, hashchk, hashstp, hashchkp.

These instructions will be used for ROP Protection.
This patch adds the four instructions.

Reviewed By: nemanjai, amyk, #powerpc

Differential Revision: https://reviews.llvm.org/D99375

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[PowerPC][NFCI] PassSubtarget to ASMWriter

Subtarget feature bits are needed to change instprinter's behavior based
on feature bits.

Most of the other popular targets were updated back in 2015,
in

[PowerPC][NFCI] PassSubtarget to ASMWriter

Subtarget feature bits are needed to change instprinter's behavior based
on feature bits.

Most of the other popular targets were updated back in 2015,
in https://reviews.llvm.org/rGb46d0234a6969
we should update it too.

Reviewed By: sfertile

Differential Revision: https://reviews.llvm.org/D94449

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[PowerPC] Delete remnant isOSDarwin references

[PowerPC] Add support for intrinsics dcbfps and dcbstps in P10.

Summary: This patch added support for the intrinsics llvm.ppc.dcbfps and llvm.ppc.dcbstps.
dcbfps and dcbstps are actually extended mn

[PowerPC] Add support for intrinsics dcbfps and dcbstps in P10.

Summary: This patch added support for the intrinsics llvm.ppc.dcbfps and llvm.ppc.dcbstps.
dcbfps and dcbstps are actually extended mnemonics of dcbf.
dcbfps RA,RB ---> dcbf RA,RB,4
dcbstps RA,RB ---> dcbf RA,RB,6

Reviewed By: amyk, steven.zhang

Differential Revision: https://reviews.llvm.org/D91323

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[PowerPC][PCRelative] Thread Local Storage Support for General Dynamic

This patch is the initial support for the General Dynamic Thread Local
Local Storage model to produce code sequence and relocat

[PowerPC][PCRelative] Thread Local Storage Support for General Dynamic

This patch is the initial support for the General Dynamic Thread Local
Local Storage model to produce code sequence and relocations correct
to the ABI for the model when using PC relative memory operations.

Patch by: NeHuang

Reviewed By: stefanp

Differential Revision: https://reviews.llvm.org/D82315

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Re-land "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support"

This reverts commit bf544fa1c3cb80f24d85e84559fb11193846259f.

Fixed the typo in PPCInstrInfo.cpp.

Revert "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support"

This reverts commit adffce71538e219aab4eeb024819baa7687262ff.

This is breaking test-suite, revert while investigation.

[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support

Per RFC http://lists.llvm.org/pipermail/llvm-dev/2020-April/141295.html
no one is making use of QPX/A2Q/BGQ/BGP CNK anymore.

This patch remove the suppo

[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support

Per RFC http://lists.llvm.org/pipermail/llvm-dev/2020-April/141295.html
no one is making use of QPX/A2Q/BGQ/BGP CNK anymore.

This patch remove the support of QPX/A2Q in llvm, BGQ/BGP in clang,
CNK support in openmp/polly.

Reviewed By: hfinkel

Differential Revision: https://reviews.llvm.org/D83915

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[PowerPC] Add linker opt for PC Relative GOT indirect accesses

A linker optimization is available on PowerPC for GOT indirect PCRelative loads.

The idea is that we can mark a usual GOT indirect loa

[PowerPC] Add linker opt for PC Relative GOT indirect accesses

A linker optimization is available on PowerPC for GOT indirect PCRelative loads.

The idea is that we can mark a usual GOT indirect load:

pld 3, vec@got@pcrel(0), 1
lwa 3, 4(3)

With a relocation to say that if we don't need to go through the GOT we can let
the linker further optimize this and replace a load with a nop.

pld 3, vec@got@pcrel(0), 1
.Lpcrel1:
.reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
lwa 3, 4(3)

This patch adds the logic that allows the compiler to add the R_PPC64_PCREL_OPT.

Reviewers: nemanjai, lei, hfinkel, sfertile, efriedma, tstellar, grosbach

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D79864

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[NFC][PowerPC] Remove the redundant InstAlias for OR instruction

Summary:
We have handle the InstAlias for OR instructions, but we handle it
agagin in PPCInstPrinter.cpp.
This patch is to Remove the

[NFC][PowerPC] Remove the redundant InstAlias for OR instruction

Summary:
We have handle the InstAlias for OR instructions, but we handle it
agagin in PPCInstPrinter.cpp.
This patch is to Remove the redundant InstAlias for OR instruction.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D80502

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[PowerPC][Future] Initial support for PCRel addressing for constant pool loads

Add initial support for PC Relative addressing for constant pool loads.
This includes adding a new relocation for @pcre

[PowerPC][Future] Initial support for PCRel addressing for constant pool loads

Add initial support for PC Relative addressing for constant pool loads.
This includes adding a new relocation for @pcrel and adding a new PowerPC flag
to identify PC relative addressing.

Differential Revision: https://reviews.llvm.org/D74486

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[PPCInstPrinter] Delete an unneeded overload of printBranchOperand. NFC

It was added by D76591 for migration purposes (not all
printBranchOperand users have migrated to the overload with `uint64_t A

[PPCInstPrinter] Delete an unneeded overload of printBranchOperand. NFC

It was added by D76591 for migration purposes (not all
printBranchOperand users have migrated to the overload with `uint64_t Address`).
Now that all have been migrated, the parameter can go away.

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[MCInstPrinter] Add parameter `Address` to MCInstPrinter::printAliasInstr. NFC

Follow-up of D72172.

[PPCInstPrinter] Change printBranchOperand(calltarget) to print the target address in hexadecimal form

```
// llvm-objdump -d output (before)
0: bl .-4
4: bl .+0
8: bl .+4

// llvm-objdump -d output

[PPCInstPrinter] Change printBranchOperand(calltarget) to print the target address in hexadecimal form

```
// llvm-objdump -d output (before)
0: bl .-4
4: bl .+0
8: bl .+4

// llvm-objdump -d output (after) ; GNU objdump -d
0: bl 0xfffffffc / bl 0xfffffffffffffffc
4: bl 0x4
8: bl 0xc
```

Many Operand's are not annotated as OPERAND_PCREL.
They are not affected (e.g. `b .+67108860`). I plan to fix them in future patches.

Modified test/tools/llvm-objdump/ELF/PowerPC/branch-offset.s to test
address space wraparound for powerpc32 and powerpc64.

Reviewed By: sfertile, jhenderson

Differential Revision: https://reviews.llvm.org/D76591

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[PowerPC][AIX] Fix printing of program counter for AIX assembly.

Program counter on AIX is the dollar-sign.

Differential Revision:https://reviews.llvm.org/D75627

[PowerPC][NFC] Clang-format on commit 4b414d

[PowerPC][Future] Add pld and pstd to future CPU
Add the prefixed instructions pld and pstd to future CPU. These are load and
store instructions that require new operand types that are 34 bits. This

[PowerPC][Future] Add pld and pstd to future CPU
Add the prefixed instructions pld and pstd to future CPU. These are load and
store instructions that require new operand types that are 34 bits. This patch
adds the two instructions as well as the operand types required.

Note that this patch also makes a minor change to tablegen to account for the
fact that some instructions are going to require shifts greater than 31 bits
for the new 34 bit instructions.

Differential Revision: https://reviews.llvm.org/D72574

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[PowerPC][Future] Add prefixed instruction paddi to future CPU

Future CPU will include support for prefixed instructions.
These prefixed instructions are formed by a 4 byte prefix
immediately follow

[PowerPC][Future] Add prefixed instruction paddi to future CPU

Future CPU will include support for prefixed instructions.
These prefixed instructions are formed by a 4 byte prefix
immediately followed by a 4 byte instruction effectively
making an 8 byte instruction. The new instruction paddi
is a prefixed form of addi.

This patch adds paddi and all of the support required
for that instruction. The majority of the patch deals with
supporting the new prefixed instructions. The addition of
paddi is mainly to allow for testing.

Differential Revision: https://reviews.llvm.org/D72569

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[MC] Add parameter `Address` to MCInstrPrinter::printInstruction

Follow-up of D72172.

Reviewed By: jhenderson, rnk

Differential Revision: https://reviews.llvm.org/D72180

[MC] Add parameter `Address` to MCInstPrinter::printInst

printInst prints a branch/call instruction as `b offset` (there are many
variants on various targets) instead of `b address`.

It is a conven

[MC] Add parameter `Address` to MCInstPrinter::printInst

printInst prints a branch/call instruction as `b offset` (there are many
variants on various targets) instead of `b address`.

It is a convention to use address instead of offset in most external
symbolizers/disassemblers. This difference makes `llvm-objdump -d`
output unsatisfactory.

Add `uint64_t Address` to printInst(), so that it can pass the argument to
printInstruction(). `raw_ostream &OS` is moved to the last to be
consistent with other print* methods.

The next step is to pass `Address` to printInstruction() (generated by
tablegen from the instruction set description). We can gradually migrate
targets to print addresses instead of offsets.

In any case, downstream projects which don't know `Address` can pass 0 as
the argument.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D72172

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[AIX] TOC pseudo expansion for 64bit large + 64bit small + 32bit large models

This patch provides support for peudo ops including ADDIStocHA8, ADDIStocHA, LWZtocL,
LDtoc, LDtocL for AIX, lowering th

[AIX] TOC pseudo expansion for 64bit large + 64bit small + 32bit large models

This patch provides support for peudo ops including ADDIStocHA8, ADDIStocHA, LWZtocL,
LDtoc, LDtocL for AIX, lowering them from MIR to assembly.

Differential Revision: https://reviews.llvm.org/D68341

llvm-svn: 375113

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