1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an PPC MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/PPCInstPrinter.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCInstrInfo.h"
17 #include "llvm/CodeGen/TargetOpcodes.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/raw_ostream.h"
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "asm-printer"
29 
30 // FIXME: Once the integrated assembler supports full register names, tie this
31 // to the verbose-asm setting.
32 static cl::opt<bool>
33 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
34              cl::desc("Use full register names when printing assembly"));
35 
36 // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
37 static cl::opt<bool>
38 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
39              cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
40 
41 // Prints full register names with percent symbol.
42 static cl::opt<bool>
43 FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
44                         cl::init(false),
45                         cl::desc("Prints full register names with percent"));
46 
47 #define PRINT_ALIAS_INSTR
48 #include "PPCGenAsmWriter.inc"
49 
50 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51   const char *RegName = getRegisterName(RegNo);
52   if (RegName[0] == 'q' /* QPX */) {
53     // The system toolchain on the BG/Q does not understand QPX register names
54     // in .cfi_* directives, so print the name of the floating-point
55     // subregister instead.
56     std::string RN(RegName);
57 
58     RN[0] = 'f';
59     OS << RN;
60 
61     return;
62   }
63 
64   OS << RegName;
65 }
66 
67 void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
68                                StringRef Annot, const MCSubtargetInfo &STI,
69                                raw_ostream &O) {
70   // Customize printing of the addis instruction on AIX. When an operand is a
71   // symbol reference, the instruction syntax is changed to look like a load
72   // operation, i.e:
73   //     Transform:  addis $rD, $rA, $src --> addis $rD, $src($rA).
74   if (TT.isOSAIX() &&
75       (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
76       MI->getOperand(2).isExpr()) {
77     assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&
78            "The first and the second operand of an addis instruction"
79            " should be registers.");
80 
81     assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) &&
82            "The third operand of an addis instruction should be a symbol "
83            "reference expression if it is an expression at all.");
84 
85     O << "\taddis ";
86     printOperand(MI, 0, O);
87     O << ", ";
88     printOperand(MI, 2, O);
89     O << "(";
90     printOperand(MI, 1, O);
91     O << ")";
92     return;
93   }
94 
95   // Check if the last operand is an expression with the variant kind
96   // VK_PPC_PCREL_OPT. If this is the case then this is a linker optimization
97   // relocation and the .reloc directive needs to be added.
98   unsigned LastOp = MI->getNumOperands() - 1;
99   if (MI->getNumOperands() > 1) {
100     const MCOperand &Operand = MI->getOperand(LastOp);
101     if (Operand.isExpr()) {
102       const MCExpr *Expr = Operand.getExpr();
103       const MCSymbolRefExpr *SymExpr =
104           static_cast<const MCSymbolRefExpr *>(Expr);
105 
106       if (SymExpr && SymExpr->getKind() == MCSymbolRefExpr::VK_PPC_PCREL_OPT) {
107         const MCSymbol &Symbol = SymExpr->getSymbol();
108         if (MI->getOpcode() == PPC::PLDpc) {
109           printInstruction(MI, Address, O);
110           O << "\n";
111           Symbol.print(O, &MAI);
112           O << ":";
113           return;
114         } else {
115           O << "\t.reloc ";
116           Symbol.print(O, &MAI);
117           O << "-8,R_PPC64_PCREL_OPT,.-(";
118           Symbol.print(O, &MAI);
119           O << "-8)\n";
120         }
121       }
122     }
123   }
124 
125   // Check for slwi/srwi mnemonics.
126   if (MI->getOpcode() == PPC::RLWINM) {
127     unsigned char SH = MI->getOperand(2).getImm();
128     unsigned char MB = MI->getOperand(3).getImm();
129     unsigned char ME = MI->getOperand(4).getImm();
130     bool useSubstituteMnemonic = false;
131     if (SH <= 31 && MB == 0 && ME == (31-SH)) {
132       O << "\tslwi "; useSubstituteMnemonic = true;
133     }
134     if (SH <= 31 && MB == (32-SH) && ME == 31) {
135       O << "\tsrwi "; useSubstituteMnemonic = true;
136       SH = 32-SH;
137     }
138     if (useSubstituteMnemonic) {
139       printOperand(MI, 0, O);
140       O << ", ";
141       printOperand(MI, 1, O);
142       O << ", " << (unsigned int)SH;
143 
144       printAnnotation(O, Annot);
145       return;
146     }
147   }
148 
149   if (MI->getOpcode() == PPC::RLDICR ||
150       MI->getOpcode() == PPC::RLDICR_32) {
151     unsigned char SH = MI->getOperand(2).getImm();
152     unsigned char ME = MI->getOperand(3).getImm();
153     // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
154     if (63-SH == ME) {
155       O << "\tsldi ";
156       printOperand(MI, 0, O);
157       O << ", ";
158       printOperand(MI, 1, O);
159       O << ", " << (unsigned int)SH;
160       printAnnotation(O, Annot);
161       return;
162     }
163   }
164 
165   // dcbt[st] is printed manually here because:
166   //  1. The assembly syntax is different between embedded and server targets
167   //  2. We must print the short mnemonics for TH == 0 because the
168   //     embedded/server syntax default will not be stable across assemblers
169   //  The syntax for dcbt is:
170   //    dcbt ra, rb, th [server]
171   //    dcbt th, ra, rb [embedded]
172   //  where th can be omitted when it is 0. dcbtst is the same.
173   if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
174     unsigned char TH = MI->getOperand(0).getImm();
175     O << "\tdcbt";
176     if (MI->getOpcode() == PPC::DCBTST)
177       O << "st";
178     if (TH == 16)
179       O << "t";
180     O << " ";
181 
182     bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
183     if (IsBookE && TH != 0 && TH != 16)
184       O << (unsigned int) TH << ", ";
185 
186     printOperand(MI, 1, O);
187     O << ", ";
188     printOperand(MI, 2, O);
189 
190     if (!IsBookE && TH != 0 && TH != 16)
191       O << ", " << (unsigned int) TH;
192 
193     printAnnotation(O, Annot);
194     return;
195   }
196 
197   if (MI->getOpcode() == PPC::DCBF) {
198     unsigned char L = MI->getOperand(0).getImm();
199     if (!L || L == 1 || L == 3) {
200       O << "\tdcbf";
201       if (L == 1 || L == 3)
202         O << "l";
203       if (L == 3)
204         O << "p";
205       O << " ";
206 
207       printOperand(MI, 1, O);
208       O << ", ";
209       printOperand(MI, 2, O);
210 
211       printAnnotation(O, Annot);
212       return;
213     }
214   }
215 
216   if (!printAliasInstr(MI, Address, O))
217     printInstruction(MI, Address, O);
218   printAnnotation(O, Annot);
219 }
220 
221 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
222                                            raw_ostream &O,
223                                            const char *Modifier) {
224   unsigned Code = MI->getOperand(OpNo).getImm();
225 
226   if (StringRef(Modifier) == "cc") {
227     switch ((PPC::Predicate)Code) {
228     case PPC::PRED_LT_MINUS:
229     case PPC::PRED_LT_PLUS:
230     case PPC::PRED_LT:
231       O << "lt";
232       return;
233     case PPC::PRED_LE_MINUS:
234     case PPC::PRED_LE_PLUS:
235     case PPC::PRED_LE:
236       O << "le";
237       return;
238     case PPC::PRED_EQ_MINUS:
239     case PPC::PRED_EQ_PLUS:
240     case PPC::PRED_EQ:
241       O << "eq";
242       return;
243     case PPC::PRED_GE_MINUS:
244     case PPC::PRED_GE_PLUS:
245     case PPC::PRED_GE:
246       O << "ge";
247       return;
248     case PPC::PRED_GT_MINUS:
249     case PPC::PRED_GT_PLUS:
250     case PPC::PRED_GT:
251       O << "gt";
252       return;
253     case PPC::PRED_NE_MINUS:
254     case PPC::PRED_NE_PLUS:
255     case PPC::PRED_NE:
256       O << "ne";
257       return;
258     case PPC::PRED_UN_MINUS:
259     case PPC::PRED_UN_PLUS:
260     case PPC::PRED_UN:
261       O << "un";
262       return;
263     case PPC::PRED_NU_MINUS:
264     case PPC::PRED_NU_PLUS:
265     case PPC::PRED_NU:
266       O << "nu";
267       return;
268     case PPC::PRED_BIT_SET:
269     case PPC::PRED_BIT_UNSET:
270       llvm_unreachable("Invalid use of bit predicate code");
271     }
272     llvm_unreachable("Invalid predicate code");
273   }
274 
275   if (StringRef(Modifier) == "pm") {
276     switch ((PPC::Predicate)Code) {
277     case PPC::PRED_LT:
278     case PPC::PRED_LE:
279     case PPC::PRED_EQ:
280     case PPC::PRED_GE:
281     case PPC::PRED_GT:
282     case PPC::PRED_NE:
283     case PPC::PRED_UN:
284     case PPC::PRED_NU:
285       return;
286     case PPC::PRED_LT_MINUS:
287     case PPC::PRED_LE_MINUS:
288     case PPC::PRED_EQ_MINUS:
289     case PPC::PRED_GE_MINUS:
290     case PPC::PRED_GT_MINUS:
291     case PPC::PRED_NE_MINUS:
292     case PPC::PRED_UN_MINUS:
293     case PPC::PRED_NU_MINUS:
294       O << "-";
295       return;
296     case PPC::PRED_LT_PLUS:
297     case PPC::PRED_LE_PLUS:
298     case PPC::PRED_EQ_PLUS:
299     case PPC::PRED_GE_PLUS:
300     case PPC::PRED_GT_PLUS:
301     case PPC::PRED_NE_PLUS:
302     case PPC::PRED_UN_PLUS:
303     case PPC::PRED_NU_PLUS:
304       O << "+";
305       return;
306     case PPC::PRED_BIT_SET:
307     case PPC::PRED_BIT_UNSET:
308       llvm_unreachable("Invalid use of bit predicate code");
309     }
310     llvm_unreachable("Invalid predicate code");
311   }
312 
313   assert(StringRef(Modifier) == "reg" &&
314          "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
315   printOperand(MI, OpNo+1, O);
316 }
317 
318 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
319                                        raw_ostream &O) {
320   unsigned Code = MI->getOperand(OpNo).getImm();
321   if (Code == 2)
322     O << "-";
323   else if (Code == 3)
324     O << "+";
325 }
326 
327 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
328                                        raw_ostream &O) {
329   unsigned int Value = MI->getOperand(OpNo).getImm();
330   assert(Value <= 1 && "Invalid u1imm argument!");
331   O << (unsigned int)Value;
332 }
333 
334 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
335                                        raw_ostream &O) {
336   unsigned int Value = MI->getOperand(OpNo).getImm();
337   assert(Value <= 3 && "Invalid u2imm argument!");
338   O << (unsigned int)Value;
339 }
340 
341 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
342                                        raw_ostream &O) {
343   unsigned int Value = MI->getOperand(OpNo).getImm();
344   assert(Value <= 8 && "Invalid u3imm argument!");
345   O << (unsigned int)Value;
346 }
347 
348 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
349                                        raw_ostream &O) {
350   unsigned int Value = MI->getOperand(OpNo).getImm();
351   assert(Value <= 15 && "Invalid u4imm argument!");
352   O << (unsigned int)Value;
353 }
354 
355 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
356                                        raw_ostream &O) {
357   int Value = MI->getOperand(OpNo).getImm();
358   Value = SignExtend32<5>(Value);
359   O << (int)Value;
360 }
361 
362 void PPCInstPrinter::printImmZeroOperand(const MCInst *MI, unsigned OpNo,
363                                          raw_ostream &O) {
364   unsigned int Value = MI->getOperand(OpNo).getImm();
365   assert(Value == 0 && "Operand must be zero");
366   O << (unsigned int)Value;
367 }
368 
369 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
370                                        raw_ostream &O) {
371   unsigned int Value = MI->getOperand(OpNo).getImm();
372   assert(Value <= 31 && "Invalid u5imm argument!");
373   O << (unsigned int)Value;
374 }
375 
376 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
377                                        raw_ostream &O) {
378   unsigned int Value = MI->getOperand(OpNo).getImm();
379   assert(Value <= 63 && "Invalid u6imm argument!");
380   O << (unsigned int)Value;
381 }
382 
383 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
384                                        raw_ostream &O) {
385   unsigned int Value = MI->getOperand(OpNo).getImm();
386   assert(Value <= 127 && "Invalid u7imm argument!");
387   O << (unsigned int)Value;
388 }
389 
390 // Operands of BUILD_VECTOR are signed and we use this to print operands
391 // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
392 // print as unsigned.
393 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
394                                        raw_ostream &O) {
395   unsigned char Value = MI->getOperand(OpNo).getImm();
396   O << (unsigned int)Value;
397 }
398 
399 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
400                                         raw_ostream &O) {
401   unsigned short Value = MI->getOperand(OpNo).getImm();
402   assert(Value <= 1023 && "Invalid u10imm argument!");
403   O << (unsigned short)Value;
404 }
405 
406 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
407                                         raw_ostream &O) {
408   unsigned short Value = MI->getOperand(OpNo).getImm();
409   assert(Value <= 4095 && "Invalid u12imm argument!");
410   O << (unsigned short)Value;
411 }
412 
413 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
414                                         raw_ostream &O) {
415   if (MI->getOperand(OpNo).isImm())
416     O << (short)MI->getOperand(OpNo).getImm();
417   else
418     printOperand(MI, OpNo, O);
419 }
420 
421 void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo,
422                                         raw_ostream &O) {
423   if (MI->getOperand(OpNo).isImm()) {
424     long long Value = MI->getOperand(OpNo).getImm();
425     assert(isInt<34>(Value) && "Invalid s34imm argument!");
426     O << (long long)Value;
427   }
428   else
429     printOperand(MI, OpNo, O);
430 }
431 
432 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
433                                         raw_ostream &O) {
434   if (MI->getOperand(OpNo).isImm())
435     O << (unsigned short)MI->getOperand(OpNo).getImm();
436   else
437     printOperand(MI, OpNo, O);
438 }
439 
440 void PPCInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
441                                         unsigned OpNo, raw_ostream &O) {
442   if (!MI->getOperand(OpNo).isImm())
443     return printOperand(MI, OpNo, O);
444   int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
445   if (PrintBranchImmAsAddress) {
446     uint64_t Target = Address + Imm;
447     if (!TT.isPPC64())
448       Target &= 0xffffffff;
449     O << formatHex(Target);
450   } else {
451     // Branches can take an immediate operand. This is used by the branch
452     // selection pass to print, for example `.+8` (for ELF) or `$+8` (for AIX)
453     // to express an eight byte displacement from the program counter.
454     if (!TT.isOSAIX())
455       O << ".";
456     else
457       O << "$";
458 
459     if (Imm >= 0)
460       O << "+";
461     O << Imm;
462   }
463 }
464 
465 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
466                                            raw_ostream &O) {
467   if (!MI->getOperand(OpNo).isImm())
468     return printOperand(MI, OpNo, O);
469 
470   O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
471 }
472 
473 
474 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
475                                  raw_ostream &O) {
476   unsigned CCReg = MI->getOperand(OpNo).getReg();
477   unsigned RegNo;
478   switch (CCReg) {
479   default: llvm_unreachable("Unknown CR register");
480   case PPC::CR0: RegNo = 0; break;
481   case PPC::CR1: RegNo = 1; break;
482   case PPC::CR2: RegNo = 2; break;
483   case PPC::CR3: RegNo = 3; break;
484   case PPC::CR4: RegNo = 4; break;
485   case PPC::CR5: RegNo = 5; break;
486   case PPC::CR6: RegNo = 6; break;
487   case PPC::CR7: RegNo = 7; break;
488   }
489   O << (0x80 >> RegNo);
490 }
491 
492 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
493                                     raw_ostream &O) {
494   printS16ImmOperand(MI, OpNo, O);
495   O << '(';
496   if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
497     O << "0";
498   else
499     printOperand(MI, OpNo+1, O);
500   O << ')';
501 }
502 
503 void PPCInstPrinter::printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo,
504                                            raw_ostream &O) {
505   printS34ImmOperand(MI, OpNo, O);
506   O << '(';
507   printImmZeroOperand(MI, OpNo + 1, O);
508   O << ')';
509 }
510 
511 void PPCInstPrinter::printMemRegImm34(const MCInst *MI, unsigned OpNo,
512                                         raw_ostream &O) {
513   printS34ImmOperand(MI, OpNo, O);
514   O << '(';
515   printOperand(MI, OpNo + 1, O);
516   O << ')';
517 }
518 
519 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
520                                     raw_ostream &O) {
521   // When used as the base register, r0 reads constant zero rather than
522   // the value contained in the register.  For this reason, the darwin
523   // assembler requires that we print r0 as 0 (no r) when used as the base.
524   if (MI->getOperand(OpNo).getReg() == PPC::R0)
525     O << "0";
526   else
527     printOperand(MI, OpNo, O);
528   O << ", ";
529   printOperand(MI, OpNo+1, O);
530 }
531 
532 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
533                                   raw_ostream &O) {
534   // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
535   // come at the _end_ of the expression.
536   const MCOperand &Op = MI->getOperand(OpNo);
537   const MCSymbolRefExpr *RefExp = nullptr;
538   const MCConstantExpr *ConstExp = nullptr;
539   if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
540     RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
541     ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
542   } else
543     RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
544 
545   O << RefExp->getSymbol().getName();
546   O << '(';
547   printOperand(MI, OpNo+1, O);
548   O << ')';
549   if (RefExp->getKind() != MCSymbolRefExpr::VK_None)
550     O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
551   if (ConstExp != nullptr)
552     O << '+' << ConstExp->getValue();
553 }
554 
555 /// showRegistersWithPercentPrefix - Check if this register name should be
556 /// printed with a percentage symbol as prefix.
557 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
558   if (!FullRegNamesWithPercent || TT.isOSDarwin() || TT.getOS() == Triple::AIX)
559     return false;
560 
561   switch (RegName[0]) {
562   default:
563     return false;
564   case 'r':
565   case 'f':
566   case 'q':
567   case 'v':
568   case 'c':
569     return true;
570   }
571 }
572 
573 /// getVerboseConditionalRegName - This method expands the condition register
574 /// when requested explicitly or targetting Darwin.
575 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
576                                                        unsigned RegEncoding)
577                                                        const {
578   if (!TT.isOSDarwin() && !FullRegNames)
579     return nullptr;
580   if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
581     return nullptr;
582   const char *CRBits[] = {
583     "lt", "gt", "eq", "un",
584     "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
585     "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
586     "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
587     "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
588     "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
589     "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
590     "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
591   };
592   return CRBits[RegEncoding];
593 }
594 
595 // showRegistersWithPrefix - This method determines whether registers
596 // should be number-only or include the prefix.
597 bool PPCInstPrinter::showRegistersWithPrefix() const {
598   if (TT.getOS() == Triple::AIX)
599     return false;
600   return TT.isOSDarwin() || FullRegNamesWithPercent || FullRegNames;
601 }
602 
603 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
604                                   raw_ostream &O) {
605   const MCOperand &Op = MI->getOperand(OpNo);
606   if (Op.isReg()) {
607     unsigned Reg = Op.getReg();
608     if (!ShowVSRNumsAsVR)
609       Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
610                                               Reg, OpNo);
611 
612     const char *RegName;
613     RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
614     if (RegName == nullptr)
615      RegName = getRegisterName(Reg);
616     if (showRegistersWithPercentPrefix(RegName))
617       O << "%";
618     if (!showRegistersWithPrefix())
619       RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
620 
621     O << RegName;
622     return;
623   }
624 
625   if (Op.isImm()) {
626     O << Op.getImm();
627     return;
628   }
629 
630   assert(Op.isExpr() && "unknown operand kind in printOperand");
631   Op.getExpr()->print(O, &MAI);
632 }
633 
634