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Searched refs:getDeadRegState (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp171 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
463 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1375 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2091 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLB7Rd()
2097 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLB7Rd()
2141 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRB7Rd()
2148 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRB7Rd()
2199 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB6Rd()
2204 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB6Rd()
2209 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB6Rd()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp609 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
611 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
613 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
615 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
797 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
799 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
801 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
803 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
1040 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMOV32BitImm()
2689 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
[all …]
H A DMLxExpansionPass.cpp298 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)); in ExpandFPMLxInstruction()
H A DARMLoadStoreOptimizer.cpp1742 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill)) in InsertLDR_STR()
1813 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
1814 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)) in FixInvalidRegPairOp()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h511 inline unsigned getDeadRegState(bool B) { in getDeadRegState() function
531 getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) | in getRegState()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineInstrBundle.cpp219 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | in finalizeBundle()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ExpandPseudo.cpp467 .addReg(Reg0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandMI()
469 .addReg(Reg1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandMI()
H A DX86InstrInfo.cpp1246 .addReg(Dest, RegState::Define | getDeadRegState(IsDead)) in convertToThreeAddressWithLEA()
6936 getDeadRegState(ImpOp.isDead()) | in unfoldMemoryOperand()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVExpandPseudoInsts.cpp264 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandVSetVL()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp159 getDeadRegState(DstIsDead && LastItem) | in expandMOVImm()
171 getDeadRegState(DstIsDead && LastItem) | in expandMOVImm()
582 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)); in expand_DestructiveOp()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp512 .addReg(SrcReg, RegState::Define | getDeadRegState(KillSrc)) in copyPhysReg()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1204 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) in commuteInstructionImpl()