605     MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
609     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
611       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
613       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
615       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
677   MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandVLD()
797     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
799       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
801       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
803       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
845     MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandLaneOp()
997           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
1004           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
1040     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
2538               .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2597             .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2638         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2689       MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2690         .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandMI()
2693       MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandMI()