| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 168 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass); in materialize32BitImm() 373 Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() 389 Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() 401 Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() 483 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() 512 Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); in select() 598 Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() 702 Register LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() 757 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() 871 Register TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() [all …]
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| H A D | MipsISelLowering.cpp | 1639 Register ScrReg = RegInfo.createVirtualRegister(RC); in emitSignExtendToI32InReg() 1670 Register Mask = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword() 1671 Register Mask2 = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword() 1672 Register Incr2 = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword() 1674 Register PtrLSB2 = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword() 1794 Register Off = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword() 1865 Register Scratch = MRI.createVirtualRegister(RC); in emitAtomicCmpSwap() 1919 Register Mask = RegInfo.createVirtualRegister(RC); in emitAtomicCmpSwapPartword() 1920 Register Mask2 = RegInfo.createVirtualRegister(RC); in emitAtomicCmpSwapPartword() 1981 Register Off = RegInfo.createVirtualRegister(RC); in emitAtomicCmpSwapPartword() [all …]
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| H A D | MipsMachineFunction.cpp | 57 MF.getRegInfo().createVirtualRegister(&getGlobalBaseRegClass(MF)); in getGlobalBaseReg() 83 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg() 84 Register V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
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| H A D | Mips16ISelDAGToDAG.cpp | 78 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg() 79 V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg() 80 V2 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
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| H A D | MipsSEISelLowering.cpp | 3058 Register VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() 3064 Register VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() 3127 Register RD1 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo() 3133 Register RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo() 3181 Register Wt = RegInfo.createVirtualRegister( in emitCOPY_FW() 3244 Register Wt = RegInfo.createVirtualRegister( in emitINSERT_FW() 3438 Register Wt1 = RegInfo.createVirtualRegister( in emitFILL_FW() 3441 Register Wt2 = RegInfo.createVirtualRegister( in emitFILL_FW() 3571 Register Rt = RegInfo.createVirtualRegister(RC); in emitLD_F16_PSEUDO() 3813 Register Ws1 = RegInfo.createVirtualRegister(RC); in emitFEXP2_W_1() [all …]
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| H A D | MipsSEFrameLowering.cpp | 174 Register VR = MRI.createVirtualRegister(RC); in expandLoadCCond() 189 Register VR = MRI.createVirtualRegister(RC); in expandStoreCCond() 207 Register VR0 = MRI.createVirtualRegister(RC); in expandLoadACC() 208 Register VR1 = MRI.createVirtualRegister(RC); in expandLoadACC() 232 Register VR0 = MRI.createVirtualRegister(RC); in expandStoreACC() 233 Register VR1 = MRI.createVirtualRegister(RC); in expandStoreACC() 265 Register VR0 = MRI.createVirtualRegister(RC); in expandCopyACC() 266 Register VR1 = MRI.createVirtualRegister(RC); in expandCopyACC() 540 Register VR = MF.getRegInfo().createVirtualRegister(RC); in emitPrologue()
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCExpandPseudos.cpp | 65 Register AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandStore() 90 Register Ra = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ() 91 Register Rb = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ() 118 Register R = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTTZ()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 448 PS->PoisonReg = MRI->createVirtualRegister(PS->RC); in runOnMachineFunction() 481 PS->InitialReg = MRI->createVirtualRegister(PS->RC); in runOnMachineFunction() 1534 Register TmpReg = MRI->createVirtualRegister(PS->RC); in mergePredStateIntoSP() 1554 Register PredStateReg = MRI->createVirtualRegister(PS->RC); in extractPredStateFromSP() 1555 Register TmpReg = MRI->createVirtualRegister(PS->RC); in extractPredStateFromSP() 1662 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr() 1683 Register VBStateReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr() 1713 Register VStateReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr() 1935 Register NewReg = MRI->createVirtualRegister(RC); in hardenValueInRegister() 2126 ExpectedRetAddrReg = MRI->createVirtualRegister(AddrRC); in tracePredStateThroughCall() [all …]
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| H A D | X86FastPreTileConfig.cpp | 169 Register Zmm = MRI->createVirtualRegister(&X86::VR512RegClass); in InitializeTileConfigStackSpace() 174 Register Ymm = MRI->createVirtualRegister(&X86::VR256RegClass); in InitializeTileConfigStackSpace() 184 Register Xmm = MRI->createVirtualRegister(&X86::VR128RegClass); in InitializeTileConfigStackSpace() 235 TileReg = MRI->createVirtualRegister(&RC); in reload() 240 Register StrideReg = MRI->createVirtualRegister(&X86::GR64_NOSPRegClass); in reload() 329 Register StackAddrReg = MRI->createVirtualRegister(&X86::GR64_NOSPRegClass); in convertPHI() 332 Register RowReg = MRI->createVirtualRegister(&X86::GR16RegClass); in convertPHI() 335 Register ColReg = MRI->createVirtualRegister(&X86::GR16RegClass); in convertPHI() 399 MRI->createVirtualRegister(&X86::GR64_NOSPRegClass); in convertPHI() 409 Register StrideReg = MRI->createVirtualRegister(&X86::GR64_NOSPRegClass); in convertPHI()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFrameLowering.cpp | 279 SPReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() 289 Register BasePtr = MRI.createVirtualRegister(PtrRC); in emitPrologue() 296 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() 304 Register BitmaskReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() 348 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() 354 SPReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue()
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| H A D | WebAssemblyPeephole.cpp | 67 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in maybeRewriteToDrop() 100 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
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| H A D | WebAssemblyRegisterInfo.cpp | 123 Register OffsetOp = MRI.createVirtualRegister(PtrRC); in eliminateFrameIndex() 128 FIRegOperand = MRI.createVirtualRegister(PtrRC); in eliminateFrameIndex()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 2845 Register DstElt = MRI.createVirtualRegister(EltRC); in insertSelect() 4871 Register Reg = MRI.createVirtualRegister(VRC); in legalizeOpWithMove() 4886 Register SubReg = MRI.createVirtualRegister(SubRC); in buildExtractSubReg() 5272 Register DstReg = MRI.createVirtualRegister(SRC); in readlaneVGPRToSGPR() 5277 Register NewSrcReg = MRI.createVirtualRegister(VRC); in readlaneVGPRToSGPR() 5444 Register DstReg = MRI.createVirtualRegister(DstRC); in legalizeGenericOperand() 5548 Register SRsrc = MRI.createVirtualRegister(SRsrcRC); in emitLoadSRsrcFromVGPRLoop() 6428 NewDstReg = MRI.createVirtualRegister(NewDstRC); in moveToVALU() 6509 Register CopySCC = MRI.createVirtualRegister(TC); in lowerSelect() 6930 Register NewDest = MRI.createVirtualRegister(DestRC); in splitScalar64BitXnor() [all …]
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| H A D | AMDGPUInstructionSelector.cpp | 242 Register DstReg = MRI->createVirtualRegister(&SubRC); in getSubOperand64() 362 Register DstLo = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() 363 Register DstHi = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() 1713 Register TmpReg = MRI->createVirtualRegister( in selectImageIntrinsic() 1961 Register LoReg = MRI->createVirtualRegister(DstRC); in selectG_TRUNC() 2235 Register LoReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() 2236 Register HiReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() 2605 Register HiReg = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() 2606 Register LoReg = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() 2622 MaskedLo = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() [all …]
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| H A D | SILoadStoreOptimizer.cpp | 1116 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair() 1256 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeImagePair() 1305 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeSBufferLoadImmPair() 1352 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeBufferLoadPair() 1408 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeTBufferLoadPair() 1471 Register SrcReg = MRI->createVirtualRegister(SuperRC); in mergeTBufferStorePair() 1522 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeFlatLoadPair() 1570 Register SrcReg = MRI->createVirtualRegister(SuperRC); in mergeFlatStorePair() 1769 Register SrcReg = MRI->createVirtualRegister(SuperRC); in mergeBufferStorePair() 1845 Register CarryReg = MRI->createVirtualRegister(CarryRC); in computeBase() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYRegisterInfo.cpp | 200 ? MRI.createVirtualRegister(&CSKY::GPRRegClass) in eliminateFrameIndex() 201 : MRI.createVirtualRegister(&CSKY::mGPRRegClass); in eliminateFrameIndex() 221 NewReg = MRI.createVirtualRegister(&CSKY::GPRRegClass); in eliminateFrameIndex() 225 NewReg = MRI.createVirtualRegister(&CSKY::mGPRRegClass); in eliminateFrameIndex()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | SwiftErrorValueTracking.cpp | 37 auto VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVReg() 59 Register VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVRegDefAt() 133 Register VReg = MF->getRegInfo().createVirtualRegister(RC); in createEntriesInEntryBlock() 243 UpwardsUse ? UUseVReg : MF->getRegInfo().createVirtualRegister(RC); in propagateVRegs()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZCopyPhysRegs.cpp | 82 Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass); in visitMBB() 92 Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass); in visitMBB()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 418 MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : &ARM::DPRRegClass); in createDupLane() 433 Register Out = MRI->createVirtualRegister(TRC); in createExtractSubreg() 447 Register Out = MRI->createVirtualRegister(&ARM::QPRRegClass); in createRegSequence() 465 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass); in createVExt() 477 Register Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass); in createInsertSubreg() 493 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass); in createImplicitDef()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVExtract.cpp | 71 Register ElemR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genElemLoad() 90 Register IdxR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genElemLoad() 124 Register AddrR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in runOnMachineFunction()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXCopy.cpp | 105 Register NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock() 127 Register NewVReg = MRI.createVirtualRegister(DstRC); in processBlock()
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| H A D | PPCRegisterInfo.cpp | 725 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc() 814 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in prepareDynamicAlloca() 822 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in prepareDynamicAlloca() 831 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca() 839 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca() 947 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling() 992 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore() 1106 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRBitSpilling() 1607 Register SRegHi = MF.getRegInfo().createVirtualRegister(RC), in eliminateFrameIndex() 1608 SReg = MF.getRegInfo().createVirtualRegister(RC); in eliminateFrameIndex() [all …]
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| H A D | PPCCTRLoops.cpp | 249 MRI->createVirtualRegister(Is64Bit ? &PPC::G8RC_and_G8RC_NOX0RegClass in expandNormalLoops() 261 MRI->createVirtualRegister(Is64Bit ? &PPC::G8RC_and_G8RC_NOX0RegClass in expandNormalLoops() 294 Register CMPDef = MRI->createVirtualRegister(&PPC::CRRCRegClass); in expandNormalLoops()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.cpp | 210 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in eliminateFrameIndex() 235 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in eliminateFrameIndex() 257 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); in eliminateFrameIndex() 278 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); in eliminateFrameIndex()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 343 Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction() 349 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction() 357 Register Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction()
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