154         Register MaskedReg = MRI->createVirtualRegister(SrcRC);  in selectCOPY()
242   Register DstReg = MRI->createVirtualRegister(&SubRC);  in getSubOperand64()
339     Register UnusedCarry = MRI->createVirtualRegister(TRI.getWaveMaskRegClass());  in selectG_ADD_SUB()
362   Register DstLo = MRI->createVirtualRegister(&HalfRC);  in selectG_ADD_SUB()
363   Register DstHi = MRI->createVirtualRegister(&HalfRC);  in selectG_ADD_SUB()
374     Register CarryReg = MRI->createVirtualRegister(CarryRC);  in selectG_ADD_SUB()
381       .addDef(MRI->createVirtualRegister(CarryRC), RegState::Dead)  in selectG_ADD_SUB()
830   Register InterpMov = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectInterpP1F16()
1457     Register M0Base = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectDSGWSIntrinsic()
1713       Register TmpReg = MRI->createVirtualRegister(  in selectImageIntrinsic()
1774     Register Zero = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectImageIntrinsic()
1788       Register Undef = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectImageIntrinsic()
1961     Register LoReg = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
1962     Register HiReg = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
1982       Register TmpReg0 = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
1983       Register TmpReg1 = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
1984       Register ImmReg = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
2091     Register UndefReg = MRI->createVirtualRegister(SrcRC);  in selectG_SZA_EXT()
2149       Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);  in selectG_SZA_EXT()
2150       Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_SZA_EXT()
2235     Register LoReg = MRI->createVirtualRegister(RC);  in selectG_CONSTANT()
2236     Register HiReg = MRI->createVirtualRegister(RC);  in selectG_CONSTANT()
2290   Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2291   Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2292   Register ConstReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2293   Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2327   Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2328   Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2329   Register ConstReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2330   Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2509       Register TmpReg = MRI->createVirtualRegister(TRI.getBoolRC());  in selectG_BRCOND()
2605   Register HiReg = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2606   Register LoReg = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2621     Register MaskLo = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2622     MaskedLo = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2635     Register MaskHi = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2636     MaskedHi = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
2947         Register TmpReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectG_SHUFFLE_VECTOR()
2976         Register TmpReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectG_SHUFFLE_VECTOR()
3002         Register TmpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_SHUFFLE_VECTOR()
3080     Register IdxReg = MRI->createVirtualRegister(TRI.getVGPR64Class());  in selectAMDGPU_BUFFER_ATOMIC_FADD()
3194     Register IdxReg = MRI->createVirtualRegister(TRI.getVGPR64Class());  in selectBufferLoadLds()
3304       VOffset = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectGlobalLoadLds()
3887     *SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectSmrdOffset()
4046                 MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectGlobalSAddr()
4112   Register VOffset = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectGlobalSAddr()
4165       SAddr = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectScratchSAddr()
4260     Register HighBits = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectMUBUFScratchOffen()
4562   Register RSrc2 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);  in buildRSRC()
4563   Register RSrc3 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);  in buildRSRC()
4564   Register RSrcHi = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);  in buildRSRC()
4565   Register RSrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);  in buildRSRC()
4586     RSrcLo = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);  in buildRSRC()
4671   SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in splitIllegalMUBUFOffset()