| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 135 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); in selectCOPY()
192 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI); in selectCOPY()
232 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in selectPHI()
398 if (!RBI.constrainGenericRegister(DstReg, RC, *MRI)) in selectG_ADD_SUB()
557 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectG_MERGE_VALUES()
1272 !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) in selectReturnAddress()
1452 if (!RBI.constrainGenericRegister(BaseOffset, in selectDSGWSIntrinsic()
2542 return RBI.constrainGenericRegister( in selectG_GLOBAL_VALUE()
2899 if (!RBI.constrainGenericRegister(DstReg, RC, *MRI) || in selectG_SHUFFLE_VECTOR()
2900 !RBI.constrainGenericRegister(SrcVec, RC, *MRI)) in selectG_SHUFFLE_VECTOR()
[all …]
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| H A D | AMDGPURegisterBankInfo.cpp | 720 constrainGenericRegister(SrcPart, AMDGPU::VGPR_32RegClass, MRI); in buildReadFirstLane()
1854 return constrainGenericRegister(DstReg, AMDGPU::VGPR_32RegClass, MRI) && in buildVCopy()
1855 constrainGenericRegister(SrcReg, AMDGPU::SReg_32RegClass, MRI); in buildVCopy()
1874 return constrainGenericRegister(SrcReg, AMDGPU::SReg_64RegClass, MRI) && in buildVCopy()
1875 constrainGenericRegister(DstReg, AMDGPU::VReg_64RegClass, MRI); in buildVCopy()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 301 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
698 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in selectTurnIntoCOPY()
699 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectTurnIntoCOPY()
761 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in selectTruncOrPtrToInt()
762 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectTruncOrPtrToInt()
871 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in selectAnyext()
872 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectAnyext()
986 RBI.constrainGenericRegister( in selectFCmp()
1178 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in emitExtractSubreg()
1179 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in emitExtractSubreg()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 983 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
2841 RBI.constrainGenericRegister(Copy, *RC, MRI); in select()
3405 RBI.constrainGenericRegister(DstReg, *DstRC, MRI); in select()
3940 RBI.constrainGenericRegister(DstReg, *SrcRC, MRI); in selectVectorICmp()
4106 RBI.constrainGenericRegister(*DstReg, *DstRC, MRI); in emitExtractVectorElt()
4126 RBI.constrainGenericRegister(*DstReg, *DstRC, MRI); in emitExtractVectorElt()
4312 RBI.constrainGenericRegister(CopyTo, *RC, MRI); in selectUnmergeValues()
5366 RBI.constrainGenericRegister(DstReg, *RC, MRI); in selectInsertElt()
5410 RBI.constrainGenericRegister( in emitConstantVector()
5483 return RBI.constrainGenericRegister(Dst, *DstRC, MRI); in tryOptBuildVecToSubregToReg()
[all …]
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 646 constrainGenericRegister(Register Reg, const TargetRegisterClass &RC,
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 223 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
1147 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in select()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 112 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
436 return RBI.constrainGenericRegister(DestReg, *DefRC, MRI); in select()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | RegisterBankInfo.cpp | 129 const TargetRegisterClass *RegisterBankInfo::constrainGenericRegister( in constrainGenericRegister() function in RegisterBankInfo
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 45 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
|