115   return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) &&  in constrainCopyLikeIntrin()
116          RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI);  in constrainCopyLikeIntrin()
135       return RBI.constrainGenericRegister(DstReg, *RC, *MRI);  in selectCOPY()
140       if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI))  in selectCOPY()
178     if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI))  in selectCOPY()
192     RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI);  in selectCOPY()
232   return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI);  in selectPHI()
398   if (!RBI.constrainGenericRegister(DstReg, RC, *MRI))  in selectG_ADD_SUB()
447   if (!RBI.constrainGenericRegister(Dst0Reg, AMDGPU::SReg_32RegClass, *MRI) ||  in selectG_UADDO_USUBO_UADDE_USUBE()
448       !RBI.constrainGenericRegister(Src0Reg, AMDGPU::SReg_32RegClass, *MRI) ||  in selectG_UADDO_USUBO_UADDE_USUBE()
449       !RBI.constrainGenericRegister(Src1Reg, AMDGPU::SReg_32RegClass, *MRI))  in selectG_UADDO_USUBO_UADDE_USUBE()
453       !RBI.constrainGenericRegister(I.getOperand(4).getReg(),  in selectG_UADDO_USUBO_UADDE_USUBE()
501   if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))  in selectG_EXTRACT()
553     if (SrcRC && !RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI))  in selectG_MERGE_VALUES()
557   if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))  in selectG_MERGE_VALUES()
582   if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))  in selectG_UNMERGE_VALUES()
596     if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))  in selectG_UNMERGE_VALUES()
601     if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI))  in selectG_UNMERGE_VALUES()
646       return RBI.constrainGenericRegister(Dst, AMDGPU::SReg_32RegClass, *MRI);  in selectG_BUILD_VECTOR_TRUNC()
656     return RBI.constrainGenericRegister(Dst, AMDGPU::SReg_32RegClass, *MRI) &&  in selectG_BUILD_VECTOR_TRUNC()
657            RBI.constrainGenericRegister(Src0, AMDGPU::SReg_32RegClass, *MRI);  in selectG_BUILD_VECTOR_TRUNC()
720       (RC && RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI))) {  in selectG_IMPLICIT_DEF()
772   if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||  in selectG_INSERT()
773       !RBI.constrainGenericRegister(Src0Reg, *Src0RC, *MRI) ||  in selectG_INSERT()
774       !RBI.constrainGenericRegister(Src1Reg, *Src1RC, *MRI))  in selectG_INSERT()
818   if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI) ||  in selectInterpP1F16()
819       !RBI.constrainGenericRegister(Dst, AMDGPU::VGPR_32RegClass, *MRI) ||  in selectInterpP1F16()
820       !RBI.constrainGenericRegister(Src0, AMDGPU::VGPR_32RegClass, *MRI))  in selectInterpP1F16()
899       RBI.constrainGenericRegister(LaneSelect, AMDGPU::SReg_32_XM0RegClass, *MRI);  in selectWritelane()
1118         RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32RegClass, *MRI);  in selectG_ICMP()
1131   RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(),  in selectG_ICMP()
1156     if (!RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(),  in selectIntrinsicIcmp()
1170   RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(), *TRI.getBoolRC(),  in selectIntrinsicIcmp()
1213   if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))  in selectRelocConstant()
1272       !RBI.constrainGenericRegister(DstReg, *RC, *MRI))  in selectReturnAddress()
1369   if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI))  in selectDSOrderedIntrinsic()
1446       if (!RBI.constrainGenericRegister(BaseOffset, AMDGPU::VGPR_32RegClass, *MRI))  in selectDSGWSIntrinsic()
1452       if (!RBI.constrainGenericRegister(BaseOffset,  in selectDSGWSIntrinsic()
1475     if (!RBI.constrainGenericRegister(VSrc, AMDGPU::VGPR_32RegClass, *MRI))  in selectDSGWSIntrinsic()
1509   if (!RBI.constrainGenericRegister(PtrBase, AMDGPU::SReg_32RegClass, *MRI))  in selectDSAppendConsume()
1951   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||  in selectG_TRUNC()
1952       !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) {  in selectG_TRUNC()
2029       if (!RBI.constrainGenericRegister(SrcReg, *SrcWithSubRC, *MRI))  in selectG_TRUNC()
2100     return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) &&  in selectG_SZA_EXT()
2101            RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI);  in selectG_SZA_EXT()
2131     if (!RBI.constrainGenericRegister(SrcReg, SrcRC, *MRI))  in selectG_SZA_EXT()
2140       return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI);  in selectG_SZA_EXT()
2165       return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, *MRI);  in selectG_SZA_EXT()
2180     return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI);  in selectG_SZA_EXT()
2258   return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI);  in selectG_CONSTANT()
2284   if (!RBI.constrainGenericRegister(Src, AMDGPU::SReg_64RegClass, *MRI) ||  in selectG_FNEG()
2285       !RBI.constrainGenericRegister(Dst, AMDGPU::SReg_64RegClass, *MRI))  in selectG_FNEG()
2332   if (!RBI.constrainGenericRegister(Src, AMDGPU::SReg_64RegClass, *MRI) ||  in selectG_FABS()
2333       !RBI.constrainGenericRegister(Dst, AMDGPU::SReg_64RegClass, *MRI))  in selectG_FABS()
2542   return RBI.constrainGenericRegister(  in selectG_GLOBAL_VALUE()
2589   if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||  in selectG_PTRMASK()
2590       !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||  in selectG_PTRMASK()
2591       !RBI.constrainGenericRegister(MaskReg, *MaskRC, *MRI))  in selectG_PTRMASK()
2706   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||  in selectG_EXTRACT_VECTOR_ELT()
2707       !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||  in selectG_EXTRACT_VECTOR_ELT()
2708       !RBI.constrainGenericRegister(IdxReg, AMDGPU::SReg_32RegClass, *MRI))  in selectG_EXTRACT_VECTOR_ELT()
2787   if (!RBI.constrainGenericRegister(VecReg, *VecRC, *MRI) ||  in selectG_INSERT_VECTOR_ELT()
2788       !RBI.constrainGenericRegister(DstReg, *VecRC, *MRI) ||  in selectG_INSERT_VECTOR_ELT()
2789       !RBI.constrainGenericRegister(ValReg, *ValRC, *MRI) ||  in selectG_INSERT_VECTOR_ELT()
2790       !RBI.constrainGenericRegister(IdxReg, AMDGPU::SReg_32RegClass, *MRI))  in selectG_INSERT_VECTOR_ELT()
2892     return RBI.constrainGenericRegister(DstReg, RC, *MRI);  in selectG_SHUFFLE_VECTOR()
2899   if (!RBI.constrainGenericRegister(DstReg, RC, *MRI) ||  in selectG_SHUFFLE_VECTOR()
2900       !RBI.constrainGenericRegister(SrcVec, RC, *MRI))  in selectG_SHUFFLE_VECTOR()
3425   if (!RBI.constrainGenericRegister(DstReg, RC, *MRI))  in selectWaveAddress()