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Searched refs:computeRegisterLiveness (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp60 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I) in copyPhysReg()
H A DARMLoadStoreOptimizer.cpp639 (MBB.computeRegisterLiveness(TRI, ARM::CPSR, InsertBefore, 20) == in CreateLoadStoreMulti()
H A DARMBaseInstrInfo.cpp2607 MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) != in tryFoldSPUpdateIntoPushPop()
5097 MI.getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI); in getImplicitSPRUseForDPRUse()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp568 MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I) != in optTwoAddrLEA()
708 MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I, 4) != in processInstructionForSlowLEA()
760 MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I, 4) != in processInstrForSlow3OpLEA()
H A DX86InstrInfo.cpp914 if (ClobbersEFLAGS && MBB.computeRegisterLiveness(&TRI, X86::EFLAGS, I) != in reMaterialize()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineBasicBlock.h1063 LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIPeepholeSDWA.cpp886 auto Liveness = MBB.computeRegisterLiveness(TRI, AMDGPU::VCC, MI, 25); in pseudoOpConvertToVOP2()
H A DSIFoldOperands.cpp238 auto Liveness = MBB->computeRegisterLiveness(&TRI, AMDGPU::VCC, MI, 16); in updateOperand()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineBasicBlock.cpp1485 MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI, in computeRegisterLiveness() function in MachineBasicBlock