Searched refs:buildUndef (Results 1 – 15 of 15) sorted by relevance
79 auto Undef0 = CSEB.buildUndef(s32); in TEST_F()80 auto Undef1 = CSEB.buildUndef(s32); in TEST_F()137 auto Undef0 = CSEB.buildUndef(s16); in TEST_F()138 auto Undef1 = CSEB.buildUndef(s16); in TEST_F()
1088 auto Op0 = B.buildUndef(S96); in TEST_F()1089 auto Op1 = B.buildUndef(S96); in TEST_F()1125 auto Op0 = B.buildUndef(S96); in TEST_F()1126 auto Op1 = B.buildUndef(S96); in TEST_F()1162 auto Op0 = B.buildUndef(S96); in TEST_F()1163 auto Op1 = B.buildUndef(S96); in TEST_F()1199 auto Op0 = B.buildUndef(S96); in TEST_F()1238 auto Op2 = B.buildUndef(S1); in TEST_F()1277 auto Op2 = B.buildUndef(S1); in TEST_F()1316 auto Op2 = B.buildUndef(S1); in TEST_F()[all …]
312 auto Ptr = B.buildUndef(P0); in TEST_F()
211 auto PtrAdd = B.buildPtrAdd(p0, {B.buildUndef(p0)}, Copies[0]); in TEST_F()667 Register Undef = B.buildUndef(s64).getReg(0); in TEST_F()
641 B.buildUndef(R); in lowerFormalArguments()821 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()826 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()914 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
2044 B.buildUndef(Dst); in legalizeAddrSpaceCast()2359 B.buildUndef(Dst); in legalizeExtractVectorElt()2401 B.buildUndef(Dst); in legalizeInsertVectorElt()2542 B.buildUndef(DstReg); in legalizeGlobalValue()3321 B.buildUndef(DstReg); in loadInputValue()3364 B.buildUndef(DstReg); in legalizeWorkitemIDIntrinsic()4346 PackedRegs.resize(2, B.buildUndef(S32).getReg(0)); in handleD16VData()4831 auto Undef = B.buildUndef(S32); in convertImageAddrToPacked()4902 B.buildUndef(MI.getOperand(0)); in legalizeImageIntrinsic()5172 Register Undef = B.buildUndef(Ty).getReg(0); in legalizeImageIntrinsic()[all …]
1921 B.buildUndef(Hi32Reg); in extendLow32IntoHigh32()
232 Register Undef = buildUndef(Op0Ty.getElementType()).getReg(0); in buildPadVectorWithUndefElements()586 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) { in buildUndef() function in MachineIRBuilder675 auto UndefVec = buildUndef(DstTy); in buildShuffleSplat()
361 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in buildLCMMergePieces()406 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); in buildLCMMergePieces()934 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); in narrowScalar()1590 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues()3970 MIRBuilder.buildUndef(DstReg); in fewerElementsVectorExtractInsertVectorElt()4357 SVOps.push_back(MIRBuilder.buildUndef(EltTy).getReg(0)); in fewerElementsVectorShuffle()4376 Output = MIRBuilder.buildUndef(NarrowTy).getReg(0); in fewerElementsVectorShuffle()4381 ? MIRBuilder.buildUndef(NarrowTy).getReg(0) in fewerElementsVectorShuffle()4905 Elts.push_back(MIRBuilder.buildUndef(MoreTy.getScalarType())); in moreElementsVector()6655 Val = MIRBuilder.buildUndef(DstTy).getReg(0); in lowerShuffleVector()[all …]
254 Undef = Builder.buildUndef(OpType.getScalarType()); in matchCombineConcatVectors()287 Builder.buildUndef(NewDstReg); in applyCombineConcatVectors()368 UndefReg = Builder.buildUndef(SrcType).getReg(0); in matchCombineShuffleVector()1798 B.buildUndef(DstReg); in matchCombineUnmergeUndef()2536 Builder.buildUndef(MI.getOperand(0)); in replaceInstWithUndef()2610 UndefReg = Builder.buildUndef(DstTy.getScalarType()).getReg(0); in applyCombineInsertVecElts()
2184 MIRBuilder.buildUndef(Undef); in translateKnownIntrinsic()2665 MIRBuilder.buildUndef(Undef); in translateLandingPad()3032 EntryBuilder->buildUndef(Reg); in translate()
524 Register Undef = B.buildUndef(SrcTy).getReg(0); in buildCopyToRegs()
413 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()425 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()
711 auto Undef = B.buildUndef(SrcTy); in applyDupLane()
957 MachineInstrBuilder buildUndef(const DstOp &Res);