Lines Matching refs:buildUndef

361       PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0);  in buildLCMMergePieces()
406         AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0);  in buildLCMMergePieces()
923       Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0);  in narrowScalar()
934       DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0));  in narrowScalar()
1590     Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);  in widenScalarMergeValues()
3970       MIRBuilder.buildUndef(DstReg);  in fewerElementsVectorExtractInsertVectorElt()
4357           SVOps.push_back(MIRBuilder.buildUndef(EltTy).getReg(0));  in fewerElementsVectorShuffle()
4376       Output = MIRBuilder.buildUndef(NarrowTy).getReg(0);  in fewerElementsVectorShuffle()
4381                          ? MIRBuilder.buildUndef(NarrowTy).getReg(0)  in fewerElementsVectorShuffle()
4905       Elts.push_back(MIRBuilder.buildUndef(MoreTy.getScalarType()));  in moreElementsVector()
6655       Val = MIRBuilder.buildUndef(DstTy).getReg(0);  in lowerShuffleVector()
6670         Undef = MIRBuilder.buildUndef(EltTy).getReg(0);  in lowerShuffleVector()