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Searched refs:buildInstr (Results 1 – 25 of 39) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h374 MachineInstrBuilder buildInstr(unsigned Opcode) { in buildInstr() function
587 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut}, in buildUAdde()
595 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut}, in buildUSube()
603 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut}, in buildSAdde()
611 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut}, in buildSSube()
669 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src}); in buildBitcast()
859 return buildInstr(Opc, Res, Op).addImm(Val); in buildAssertOp()
1641 return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0}); in buildCTLZ()
1651 return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0}); in buildCTTZ()
1806 return buildInstr(TargetOpcode::G_ABS, {Dst}, {Src}); in buildAbs()
[all …]
H A DCSEMIRBuilder.h94 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DCSETest.cpp23 auto MIBInput = B.buildInstr(TargetOpcode::G_TRUNC, {s16}, {Copies[0]}); in TEST_F()
24 auto MIBInput1 = B.buildInstr(TargetOpcode::G_TRUNC, {s16}, {Copies[1]}); in TEST_F()
35 CSEB.buildInstr(TargetOpcode::G_ADD, {AddReg}, {MIBInput, MIBInput}); in TEST_F()
38 CSEB.buildInstr(TargetOpcode::G_ADD, {s16}, {MIBInput, MIBInput}); in TEST_F()
41 CSEB.buildInstr(TargetOpcode::G_ADD, {s16}, {MIBInput, MIBInput}); in TEST_F()
44 CSEB.buildInstr(TargetOpcode::G_ADD, {s16}, {MIBInput, MIBInput1}); in TEST_F()
94 auto NonCSEFMul = RegularBuilder.buildInstr(TargetOpcode::G_AND) in TEST_F()
102 auto ExtractMIB = CSEB.buildInstr(TargetOpcode::G_EXTRACT, {s16}, in TEST_F()
104 auto ExtractMIB1 = CSEB.buildInstr(TargetOpcode::G_EXTRACT, {s16}, in TEST_F()
106 auto ExtractMIB2 = CSEB.buildInstr(TargetOpcode::G_EXTRACT, {s16}, in TEST_F()
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H A DLegalizerHelperTest.cpp40 auto ROTR = B.buildInstr(TargetOpcode::G_ROTR, {S32}, {Src, Amt}); in TEST_F()
41 auto ROTL = B.buildInstr(TargetOpcode::G_ROTL, {S32}, {Src, Amt}); in TEST_F()
433 auto MIBCTTZ = B.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, in TEST_F()
1054 B.buildInstr(TargetOpcode::G_UMULO, {s64, LLT::scalar(1)}, in TEST_F()
1520 auto Phi = B.buildInstr(TargetOpcode::G_PHI) in TEST_F()
1529 B.buildInstr(TargetOpcode::G_PHI) in TEST_F()
1910 auto MIB = B.buildInstr( in TEST_F()
1943 auto MIB = B.buildInstr( in TEST_F()
1975 auto MIB = B.buildInstr( in TEST_F()
2009 auto MIB = B.buildInstr( in TEST_F()
[all …]
H A DConstantFoldingTest.cpp35 CFB.buildInstr(TargetOpcode::G_ADD, {s32}, in TEST_F()
47 CFB1.buildInstr(TargetOpcode::G_SUB, {s32}, in TEST_F()
55 CFB1.buildInstr(TargetOpcode::G_SEXT_INREG, {s32}, in TEST_F()
63 CFB1.buildInstr(TargetOpcode::G_SEXT_INREG, {s32}, in TEST_F()
H A DPatternMatchTest.cpp158 auto MIBFMul = B.buildInstr(TargetOpcode::G_FMUL, {s64}, in TEST_F()
168 auto MIBFSub = B.buildInstr(TargetOpcode::G_FSUB, {s64}, in TEST_F()
336 auto MIBFabs = B.buildInstr(TargetOpcode::G_FABS, {s32}, {Copy0s32}); in TEST_F()
342 auto MIBFNeg = B.buildInstr(TargetOpcode::G_FNEG, {s32}, {Copy0s32}); in TEST_F()
521 B.buildInstr(TargetOpcode::DBG_VALUE, {}, {Reg}); in TEST_F()
522 B.buildInstr(TargetOpcode::DBG_VALUE, {}, {Reg}); in TEST_F()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp83 return buildInstr(TargetOpcode::DBG_VALUE) in buildFIDbgValue()
119 auto MIB = buildInstr(TargetOpcode::DBG_LABEL); in buildDbgLabel()
272 return buildInstr(TargetOpcode::G_BRJT) in buildBrJT()
391 auto MIB = buildInstr(Opcode); in buildLoadInstr()
421 auto MIB = buildInstr(TargetOpcode::G_STORE); in buildStore()
473 return buildInstr(ExtOp, Res, Op); in buildBoolExt()
514 return buildInstr(Opcode, Res, Op); in buildExtOrTrunc()
558 return buildInstr(Opcode, Dst, Src); in buildCast()
866 auto MIB = buildInstr(Opcode); in buildAtomicRMW()
973 return buildInstr(TargetOpcode::G_FENCE) in buildFence()
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H A DCSEMIRBuilder.cpp170 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc, in buildInstr() function in CSEMIRBuilder
278 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
282 auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
299 MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
H A DLegalizerHelper.cpp1353 .buildInstr( in narrowScalar()
1452 MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt}); in widenScalarDst()
1461 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc}); in narrowScalarDst()
4484 .buildInstr(ScalarOpc, {NarrowTy}, in fewerElementsVectorReductions()
4523 MIRBuilder.buildInstr(ScalarOpc, {DstReg}, in fewerElementsVectorReductions()
5104 MIRBuilder.buildInstr(OpO, {DstReg, CarryOut}, in narrowScalarAddSub()
5107 MIRBuilder.buildInstr(OpF, {DstReg, CarryOut}, in narrowScalarAddSub()
5361 auto Inst = MIRBuilder.buildInstr( in narrowScalarBasic()
5849 MIRBuilder.buildInstr(RevRot, {Dst}, {Src, Neg}); in lowerRotateWithReverseRotate()
7268 MIRBuilder.buildInstr( in lowerDIVREM()
[all …]
H A DIRTranslator.cpp304 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags); in translateBinaryOp()
317 MIRBuilder.buildInstr(Opcode, {Res}, {Op0}, Flags); in translateUnaryOp()
1480 MIRBuilder.buildInstr(Opcode, {Res}, {Op}); in translateCast()
1607 auto ICall = MIRBuilder.buildInstr(Opcode); in translateMemFunc()
1698 MIRBuilder.buildInstr( in translateOverflowIntrinsic()
1711 MIRBuilder.buildInstr(Op, {Dst}, { Src0, Src1, Scale }); in translateFixedPointIntrinsic()
1831 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs, in translateSimpleIntrinsic()
2177 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)}, in translateKnownIntrinsic()
2215 MIRBuilder.buildInstr(TargetOpcode::G_WRITE_REGISTER) in translateKnownIntrinsic()
2275 auto Rdx = MIRBuilder.buildInstr( in translateKnownIntrinsic()
[all …]
H A DCombinerHelper.cpp1074 auto MIB = MIRBuilder.buildInstr(NewOpcode); in applyCombineIndexedLoadStore()
1179 Builder.buildInstr(IsSigned ? TargetOpcode::G_SDIVREM in applyCombineDivRem()
1585 .buildInstr(Opcode, {DestType}, in applyShiftOfShiftedLogic()
2181 Builder.buildInstr(SrcExtOp, {DstReg}, {Reg}); in applyCombineExtOfExt()
2257 Builder.buildInstr(SrcExtOp, {DstReg}, {SrcReg}); in applyCombineTruncOfExt()
4083 B.buildInstr(FshOpc, {Dst}, {ShlSrc, LShrSrc, Amt}); in matchOrShiftToFunnelShift()
4383 B.buildInstr(ExtrOpcode, {Dst}, {ShlSrc, PosCst, WidthCst}); in matchBitfieldExtractFromShr()
5093 B.buildInstr(PreferredFusedOpcode, {MI.getOperand(0).getReg()}, in matchCombineFAddFMulToFMadOrFMA()
5228 B.buildInstr(PreferredFusedOpcode, {InnerFMA}, {U, V, Z}); in matchCombineFAddFMAFMulToFMadOrFMA()
5275 B.buildInstr(PreferredFusedOpcode, {MI.getOperand(0).getReg()}, in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp399 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, MatchInfo.SrcOps); in applyShuffleVectorPseudo()
412 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, in applyEXT()
507 MIB.buildInstr(NewOpc, {MI.getOperand(0)}, {MI.getOperand(1), ImmDef}); in applyVAshrLshrImm()
717 B.buildInstr(MatchInfo.first, {MI.getOperand(0).getReg()}, {DupSrc, Lane}); in applyDupLane()
739 B.buildInstr(AArch64::G_DUP, {MI.getOperand(0).getReg()}, in applyBuildVectorToDup()
868 ? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS}) in getVectorFCMP()
876 : MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS}) in getVectorFCMP()
883 : MIB.buildInstr(AArch64::G_FCMGE, {DstTy}, {LHS, RHS}) in getVectorFCMP()
890 : MIB.buildInstr(AArch64::G_FCMGT, {DstTy}, {LHS, RHS}) in getVectorFCMP()
897 : MIB.buildInstr(AArch64::G_FCMGE, {DstTy}, {RHS, LHS}) in getVectorFCMP()
[all …]
H A DAArch64InstructionSelector.cpp1735 auto Bcc = MIB.buildInstr(AArch64::Bcc) in selectCompareBranch()
3580 MIB.buildInstr(Mopcode, {DefDstPtr, DefSize}, in selectMOPS()
3607 MIB.buildInstr(AArch64::BR, {}, {TargetReg}); in selectBrJT()
3652 MIB.buildInstr(getBLRCallOpcode(MF), {}, {Load}) in selectTLSGlobalValue()
3935 Cmp = MIB.buildInstr(NotOpc, {DstReg}, {Cmp}); in selectVectorICmp()
5182 auto TBL1 = MIB.buildInstr( in selectShuffleVector()
5580 auto Load = MIB.buildInstr(Opc, {Ty}, {Ptr}); in selectVectorLoadIntrinsic()
5611 auto NewI = MIB.buildInstr( in selectIntrinsicWithSideEffects()
5626 MIB.buildInstr(AArch64::BRK, {}, {}) in selectIntrinsicWithSideEffects()
5840 MIB.buildInstr(AArch64::XPACLRI); in selectIntrinsic()
[all …]
H A DAArch64LegalizerInfo.cpp954 auto ADRP = MIRBuilder.buildInstr(AArch64::ADRP, {LLT::pointer(0, 64)}, {}) in legalizeSmallCMGlobalValue()
975 ADRP = MIRBuilder.buildInstr(AArch64::MOVKXi, {LLT::pointer(0, 64)}, {ADRP}) in legalizeSmallCMGlobalValue()
982 MIRBuilder.buildInstr(AArch64::G_ADD_LOW, {DstReg}, {ADRP}) in legalizeSmallCMGlobalValue()
1099 NewI = MIRBuilder.buildInstr(AArch64::LDPXi, {s64, s64}, {}); in legalizeLoadStore()
1103 NewI = MIRBuilder.buildInstr( in legalizeLoadStore()
1335 MIRBuilder.buildInstr(TargetOpcode::REG_SEQUENCE, {CASDesired}, {}) in legalizeAtomicCmpxchg128()
1340 MIRBuilder.buildInstr(TargetOpcode::REG_SEQUENCE, {CASNew}, {}) in legalizeAtomicCmpxchg128()
1346 CAS = MIRBuilder.buildInstr(Opcode, {CASDst}, {CASDesired, CASNew, Addr}); in legalizeAtomicCmpxchg128()
1373 CAS = MIRBuilder.buildInstr(Opcode, {DstLo, DstHi, Scratch}, in legalizeAtomicCmpxchg128()
H A DAArch64CallLowering.cpp418 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}) in lowerReturn()
440 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}) in lowerReturn()
964 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN); in lowerTailCall()
1075 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(0).addImm(0); in lowerTailCall()
1148 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN); in lowerCall()
1246 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP) in lowerCall()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVCallLowering.cpp40 return MIRBuilder.buildInstr(SPIRV::OpReturnValue) in lowerReturn()
45 MIRBuilder.buildInstr(SPIRV::OpReturn); in lowerReturn()
222 MIRBuilder.buildInstr(SPIRV::OpFunction) in lowerFormalArguments()
233 MIRBuilder.buildInstr(SPIRV::OpFunctionParameter) in lowerFormalArguments()
246 auto MIB = MIRBuilder.buildInstr(SPIRV::OpEntryPoint) in lowerFormalArguments()
314 auto MIB = MIRBuilder.buildInstr(SPIRV::OpFunctionCall) in lowerCall()
H A DSPIRVGlobalRegistry.cpp75 return MIRBuilder.buildInstr(SPIRV::OpTypeBool) in getOpTypeBool()
82 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeInt) in getOpTypeInt()
91 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeFloat) in getOpTypeFloat()
98 return MIRBuilder.buildInstr(SPIRV::OpTypeVoid) in getOpTypeVoid()
110 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeVector) in getOpTypeVector()
203 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantI) in buildConstantInt()
209 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantNull) in buildConstantInt()
326 auto MIB = MIRBuilder.buildInstr(SPIRV::OpVariable) in buildGlobalVariable()
383 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeArray) in getOpTypeArray()
448 return MIRBuilder.buildInstr(SPIRV::OpTypePointer) in getOpTypePointer()
[all …]
H A DSPIRVUtils.cpp102 auto MIB = MIRBuilder.buildInstr(SPIRV::OpName).addUse(Target); in buildOpName()
119 auto MIB = MIRBuilder.buildInstr(SPIRV::OpDecorate) in buildOpDecorate()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp122 B.buildInstr(Opc, {MI.getOperand(0)}, {X, Y}, MI.getFlags()); in applySelectFCmpToFMinToFMaxLegacy()
199 B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {DstReg}, in applyUCharToFloat()
202 auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32}, in applyUCharToFloat()
294 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
H A DAMDGPUPreLegalizerCombiner.cpp137 B.buildInstr(AMDGPU::G_AMDGPU_CVT_PK_I16_I32, {V2S16}, in applyClampI64ToI16()
147 auto Med3 = B.buildInstr( in applyClampI64ToI16()
H A DAMDGPUCallLowering.cpp206 SPReg = MIRBuilder.buildInstr(AMDGPU::G_AMDGPU_WAVE_ADDRESS, {PtrTy}, in getStackAddress()
327 Reg = B.buildInstr(ExtendOp, {ExtTy}, {Reg}).getReg(0); in lowerReturnVal()
363 B.buildInstr(AMDGPU::S_ENDPGM) in lowerReturn()
1174 CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP); in lowerTailCall()
1267 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN).addImm(NumBytes).addImm(0); in lowerTailCall()
1334 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP) in lowerCall()
1415 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN) in lowerCall()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp150 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
156 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) in materialize32BitImm()
163 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
169 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {}) in materialize32BitImm()
171 MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg}) in materialize32BitImm()
604 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
617 MachineInstrBuilder PairF64 = B.buildInstr( in select()
806 MachineInstrBuilder MIB = B.buildInstr( in select()
H A DMipsLegalizerInfo.cpp469 if (!MIRBuilder.buildInstr(Opcode) in SelectMSA3OpIntrinsic()
484 MIRBuilder.buildInstr(Opcode) in MSA3OpIntrinsicToGeneric()
496 MIRBuilder.buildInstr(Opcode) in MSA2OpIntrinsicToGeneric()
513 MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP); in legalizeIntrinsic()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallLowering.cpp302 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown); in lowerCall()
344 MIRBuilder.buildInstr(X86::MOV8ri) in lowerCall()
390 MIRBuilder.buildInstr(AdjStackUp) in lowerCall()
/llvm-project-15.0.7/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp189 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown); in lowerCall()
227 MIRBuilder.buildInstr(AdjStackUp).addImm(Assigner.StackOffset).addImm(0); in lowerCall()

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