304   MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags);  in translateBinaryOp()
317   MIRBuilder.buildInstr(Opcode, {Res}, {Op0}, Flags);  in translateUnaryOp()
1480   MIRBuilder.buildInstr(Opcode, {Res}, {Op});  in translateCast()
1607   auto ICall = MIRBuilder.buildInstr(Opcode);  in translateMemFunc()
1677       MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {});  in getStackGuard()
1698   MIRBuilder.buildInstr(  in translateOverflowIntrinsic()
1711   MIRBuilder.buildInstr(Op, {Dst}, { Src0, Src1, Scale });  in translateFixedPointIntrinsic()
1831   MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs,  in translateSimpleIntrinsic()
1877   MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(FPI)}, VRegs, Flags);  in translateConstrainedFPIntrinsic()
1926       MIRBuilder.buildInstr(Op).addFrameIndex(getOrCreateFrameIndex(*AI));  in translateKnownIntrinsic()
1978     MIRBuilder.buildInstr(TargetOpcode::G_VASTART, {}, {getOrCreateVReg(*Ptr)})  in translateKnownIntrinsic()
2177     MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)},  in translateKnownIntrinsic()
2209         .buildInstr(TargetOpcode::G_READ_REGISTER, {getOrCreateVReg(CI)}, {})  in translateKnownIntrinsic()
2215     MIRBuilder.buildInstr(TargetOpcode::G_WRITE_REGISTER)  in translateKnownIntrinsic()
2260       MIRBuilder.buildInstr(Opc, {Dst}, {ScalarSrc, VecSrc},  in translateKnownIntrinsic()
2275     auto Rdx = MIRBuilder.buildInstr(  in translateKnownIntrinsic()
2277     MIRBuilder.buildInstr(ScalarOpc, {Dst}, {ScalarSrc, Rdx},  in translateKnownIntrinsic()
2309         .buildInstr(TargetOpcode::G_INTRINSIC_FPTRUNC_ROUND,  in translateKnownIntrinsic()
2578     MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);  in translateInvoke()
2590     MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);  in translateInvoke()
2654   MIRBuilder.buildInstr(TargetOpcode::EH_LABEL)  in translateLandingPad()
2754   MIRBuilder.buildInstr(TargetOpcode::G_VAARG, {getOrCreateVReg(U)},  in translateVAArg()
2835       .buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {getOrCreateVReg(U)},  in translateShuffleVector()
2847     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, {Reg}, {});  in translatePHI()