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Searched refs:buildCopy (Results 1 – 24 of 24) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp177 auto CopyLo = MIRBuilder.buildCopy(LLT::scalar(32), VALo.getLocReg()); in assignCustomValue()
178 auto CopyHi = MIRBuilder.buildCopy(LLT::scalar(32), VAHi.getLocReg()); in assignCustomValue()
223 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
236 auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP)); in getStackAddress()
283 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
284 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
288 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
289 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
430 MIRBuilder.buildCopy(RegTy, Register(ArgRegs[I])); in lowerFormalArguments()
537 MIRBuilder.buildCopy( in lowerCall()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp109 void buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, int64_t LoadDisp,
380 void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, in buildCopy() function in X86AvoidSFBPass
440 buildCopy(LoadInst, getYMMtoXMMLoadOpcode(LoadInst->getOpcode()), LdDisp, in buildCopies()
451 buildCopy(LoadInst, X86::MOV64rm, LdDisp, StoreInst, X86::MOV64mr, StDisp, in buildCopies()
461 buildCopy(LoadInst, X86::MOV32rm, LdDisp, StoreInst, X86::MOV32mr, StDisp, in buildCopies()
471 buildCopy(LoadInst, X86::MOV16rm, LdDisp, StoreInst, X86::MOV16mr, StDisp, in buildCopies()
481 buildCopy(LoadInst, X86::MOV8rm, LdDisp, StoreInst, X86::MOV8mr, StDisp, in buildCopies()
H A DX86CallLowering.cpp97 MIRBuilder.buildCopy(p0, STI.getRegisterInfo()->getStackRegister()); in getStackAddress()
111 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
/llvm-project-15.0.7/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp42 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
61 auto SPReg = MIRBuilder.buildCopy(p0, StackReg).getReg(0); in getStackAddress()
166 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp102 auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP)); in getStackAddress()
121 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
296 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
303 auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg); in assignValueToReg()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp79 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
113 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg); in assignValueToReg()
200 SPReg = MIRBuilder.buildCopy(PtrTy, in getStackAddress()
222 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
470 B.buildCopy(VReg, InputPtrReg); in allocateHSAUserSGPRs()
1141 auto ScratchRSrcReg = MIRBuilder.buildCopy(LLT::fixed_vector(4, 32), in handleImplicitCallArguments()
1143 MIRBuilder.buildCopy(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg); in handleImplicitCallArguments()
1148 MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second); in handleImplicitCallArguments()
H A DAMDGPURegisterBankInfo.cpp697 Src = B.buildCopy(Ty, Src).getReg(0); in buildReadFirstLane()
871 OpReg = B.buildCopy(OpTy, OpReg).getReg(0); in executeInWaterfallLoop()
1195 auto SPCopy = B.buildCopy(PtrTy, SPReg); in applyMappingDynStackAlloc()
1601 Register VSrc0 = B.buildCopy(S32, Src0).getReg(0); in applyMappingMAD_64_32()
1651 DstLo = B.buildCopy(S32, DstLo).getReg(0); in applyMappingMAD_64_32()
1652 DstHi = B.buildCopy(S32, DstHi).getReg(0); in applyMappingMAD_64_32()
1700 B.buildCopy(Dst1, Carry); in applyMappingMAD_64_32()
1912 B.buildCopy(Hi32Reg, Lo32Reg); in extendLow32IntoHigh32()
1997 B.buildCopy(DstReg, Res[L]); in foldExtractEltToCmpSelect()
2451 B.buildCopy(DstRegs[0], SrcRegs[0]); in applyMappingImpl()
[all …]
H A DAMDGPURegBankCombiner.cpp102 Register VgprReg = B.buildCopy(MRI.getType(Reg), Reg).getReg(0); in getAsVgpr()
H A DAMDGPULegalizerInfo.cpp1999 B.buildCopy(Dst, BuildPtr); in legalizeAddrSpaceCast()
2357 B.buildCopy(Dst, Unmerge.getReg(IdxVal)); in legalizeExtractVectorElt()
3296 B.buildCopy(DstReg, LiveIn); in loadInputValue()
5332 B.buildCopy(SGPR01, Temp); in legalizeTrapHsaQueuePtr()
5347 B.buildCopy(SGPR01, LiveIn); in legalizeTrapHsaQueuePtr()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp264 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0); in getStackAddress()
289 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
463 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg); in lowerReturn()
521 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg)); in handleMustTailForwardedRegisters()
1061 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall()
1236 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21)); in lowerCall()
H A DAArch64InstructionSelector.cpp949 auto Copy = MIB.buildCopy({DstTempRC}, {SrcReg}); in selectCopy()
2596 MIB.buildCopy({DefReg}, {DefGPRReg}); in select()
3569 MIB.buildCopy(DstPtrCopy, DstPtr); in selectMOPS()
3570 MIB.buildCopy(SrcValCopy, SrcOrVal); in selectMOPS()
3571 MIB.buildCopy(SizeCopy, Size); in selectMOPS()
3938 MIB.buildCopy(DstReg, Cmp.getReg(0)); in selectVectorICmp()
5765 MIB.buildCopy({SrcReg}, {I.getOperand(2)}); in selectIntrinsic()
5783 MIB.buildCopy({I.getOperand(0)}, {DstReg}); in selectIntrinsic()
5859 MIB.buildCopy({DstReg}, {FrameAddr}); in selectIntrinsic()
6627 auto Copy = MIB.buildCopy({&RC}, {Reg}); in moveScalarRegClass()
[all …]
H A DAArch64PostLegalizerCombiner.cpp232 B.buildCopy(DstReg, Res.getReg(0)); in matchAArch64MulConstCombine()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp265 MIRBuilder.buildCopy(Dst, Src); in buildAnyextOrCopy()
631 MIRBuilder.buildCopy(Tmp1Reg, SrcReg); in lowerInlineAsm()
635 MIRBuilder.buildCopy(ResRegs[i], SrcReg); in lowerInlineAsm()
H A DIRTranslator.cpp337 MIRBuilder.buildCopy( in translateCompare()
340 MIRBuilder.buildCopy( in translateCompare()
1299 MIRBuilder.buildCopy(Regs[0], VReg); in translateLoad()
1352 MIRBuilder.buildCopy(VReg, Vals[0]); in translateStore()
1461 MIRBuilder.buildCopy(Regs[0], Src); in translateCopy()
1577 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); in translateGetElementPtr()
2151 MIRBuilder.buildCopy(Reg, StackPtr); in translateKnownIntrinsic()
2165 MIRBuilder.buildCopy(StackPtr, Reg); in translateKnownIntrinsic()
2195 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2679 MIRBuilder.buildCopy(ResRegs[0], ExceptionReg); in translateLandingPad()
[all …]
H A DCSEMIRBuilder.cpp150 return buildCopy(Op.getReg(), MIB.getReg(0)); in generateCopiesIfRequired()
H A DCallLowering.cpp740 MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr); in handleAssignments()
1210 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
1214 auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg); in assignValueToReg()
H A DMachineIRBuilder.cpp278 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res, in buildCopy() function in MachineIRBuilder
487 return buildCopy(Res, Op); in buildBoolExtInReg()
546 return buildCopy(Dst, Src); in buildCast()
H A DLegalizerHelper.cpp4493 MIRBuilder.buildCopy(DstReg, SplitSrcs[0]); in fewerElementsVectorReductions()
4502 MIRBuilder.buildCopy(DstReg, Acc); in fewerElementsVectorReductions()
5244 MIRBuilder.buildCopy(DstReg, DstRegs[0]); in narrowScalarExtract()
6587 MIRBuilder.buildCopy(DstReg, SrcRegs[IdxVal]); in lowerExtractInsertVectorElt()
6658 MIRBuilder.buildCopy(DstReg, Val); in lowerShuffleVector()
6707 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg); in lowerDynStackAlloc()
6722 MIRBuilder.buildCopy(SPReg, SPTmp); in lowerDynStackAlloc()
6723 MIRBuilder.buildCopy(Dst, SPTmp); in lowerDynStackAlloc()
6755 MIRBuilder.buildCopy(Dst, SubVectorElts[0]); in lowerExtract()
7189 MIRBuilder.buildCopy(ValReg, PhysReg); in lowerReadWriteRegister()
[all …]
H A DCombinerHelper.cpp162 Builder.buildCopy(ToReg, FromReg); in replaceRegWith()
386 Builder.buildCopy(NewDstReg, Ops[0]); in applyCombineShuffleVector()
811 Builder.buildCopy(MI.getOperand(0).getReg(), MI.getOperand(1).getReg()); in applySextTruncSextLoad()
2018 Builder.buildCopy(DstReg, Reg); in applyCombineI2PToP2I()
4778 B.buildCopy(Dst, LHS); in matchAddOBy0()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DSplitKit.h427 SlotIndex buildCopy(Register FromReg, Register ToReg, LaneBitmask LaneMask,
H A DSplitKit.cpp537 SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg, in buildCopy() function in SplitEditor
627 Def = buildCopy(Edit->getReg(), Reg, LaneMask, MBB, I, Late, RegIdx); in defFromParent()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.cpp322 MIRBuilder.buildCopy(ResVReg, Reg); in buildGlobalVariable()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h522 Builder.buildCopy(DstReg, SrcReg); in replaceRegOrBuildCopy()
H A DMachineIRBuilder.h851 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);