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Searched refs:buildAnyExt (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DLegalizerHelperTest.cpp2153 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
2211 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
2270 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
2323 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
2376 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
2429 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
2482 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
2535 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
2583 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
2631 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
[all …]
H A DPatternMatchTest.cpp397 auto MIBAExt = B.buildAnyExt(s64, MIBTrunc); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp374 Val = MIRBuilder.buildAnyExt(s32, Val).getReg(0); in legalizeCustom()
376 Val = MIRBuilder.buildAnyExt(s64, Val).getReg(0); in legalizeCustom()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp290 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN()
H A DAMDGPUCallLowering.cpp39 return Handler.MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0); in extendRegisterMin32()
H A DAMDGPULegalizerInfo.cpp3029 Tmp = B.buildAnyExt(S64, LocalAccum[0]).getReg(0); in buildMultiply()
4333 WideRegs.push_back(B.buildAnyExt(S32, Unmerge.getReg(I)).getReg(0)); in handleD16VData()
4391 Register AnyExt = B.buildAnyExt(LLT::scalar(32), VData).getReg(0); in fixStoreSourceType()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp262 Src = MIRBuilder.buildAnyExt(LLT::scalar(DstSize), Src).getReg(0); in buildAnyextOrCopy()
H A DCallLowering.cpp488 B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i)); in buildCopyToRegs()
1141 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); in extendRegister()
H A DLegalizerHelper.cpp924 MIRBuilder.buildAnyExt(DstReg, ImplicitReg); in narrowScalar()
1043 MIRBuilder.buildAnyExt(DstReg, TmpReg); in narrowScalar()
1652 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); in widenScalarUnmergeValues()
1681 WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0); in widenScalarUnmergeValues()
1787 Src = MIRBuilder.buildAnyExt(WideTy, Src); in widenScalarExtract()
1943 auto LHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(1)); in widenScalarAddSubShlSat()
1945 : MIRBuilder.buildAnyExt(WideTy, MI.getOperand(2)); in widenScalarAddSubShlSat()
3091 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); in lowerStore()
5284 MIRBuilder.buildAnyExt(SrcReg, SrcRegs[I]); in narrowScalarInsert()
H A DMachineIRBuilder.cpp442 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res, in buildAnyExt() function in MachineIRBuilder
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1025 Register ZExtValueReg = MIB.buildAnyExt(LLT::scalar(64), Value).getReg(0); in legalizeIntrinsic()
1409 MIRBuilder.buildAnyExt(LLT::scalar(64), Value).getReg(0); in legalizeMemOps()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h629 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);