Home
last modified time | relevance | path

Searched refs:bitsGT (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DValueTypes.h256 bool bitsGT(EVT VT) const { in bitsGT() function
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp105 if (Src.getValueType().bitsGT(MVT::i32)) in EmitSpecializedLibcall()
H A DARMISelLowering.cpp12576 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineBUILD_VECTORToVPADDL()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp107 if (AVT.bitsGT(MVT::i8)) { in EmitTargetCodeForMemset()
H A DX86FastISel.cpp3625 if (DstVT.bitsGT(SrcVT)) in fastSelectInstruction()
H A DX86ISelLowering.cpp23258 if (Sign.getSimpleValueType().bitsGT(VT)) in LowerFCOPYSIGN()
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DMachineValueType.h1149 bool bitsGT(MVT VT) const { in bitsGT() function
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp394 } else if (IdxVT.bitsGT(PtrVT)) { in getRegForGEPIndex()
1785 if (DstVT.bitsGT(SrcVT)) in selectOperator()
H A DSelectionDAG.cpp1342 return VT.bitsGT(Op.getValueType()) in getFPExtendOrRound()
1353 VT.bitsGT(Op.getValueType()) in getStrictFPExtendOrRound()
1362 return VT.bitsGT(Op.getValueType()) ? in getAnyExtOrTrunc()
1368 return VT.bitsGT(Op.getValueType()) ? in getSExtOrTrunc()
1374 return VT.bitsGT(Op.getValueType()) ? in getZExtOrTrunc()
4922 if (SVT.bitsGT(VT.getScalarType())) { in foldCONCAT_VECTORS()
5287 assert(Operand.getValueType().bitsGT(VT) && in getNode()
5297 if (Operand.getOperand(0).getValueType().bitsGT(VT)) in getNode()
5733 if (ScalarVT.isInteger() && ScalarVT.bitsGT(InSVT)) { in FoldConstantArithmetic()
7113 if (MemOps[i].bitsGT(LargestVT)) in getMemsetStores()
H A DDAGCombiner.cpp5674 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound()) in isAndLoadExtLoad()
13198 if (N0.getOperand(0).getValueType().bitsGT(VT)) in visitTRUNCATE()
19662 ResultVT.bitsGT(VecEltVT) ? ISD::NON_EXTLOAD : ISD::EXTLOAD; in scalarizeExtractedVectorLoad()
19696 if (ResultVT.bitsGT(VecEltVT)) { in scalarizeExtractedVectorLoad()
19791 InOp.getValueType().bitsGT(ScalarVT)); in visitEXTRACT_VECTOR_ELT()
19963 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) in visitEXTRACT_VECTOR_ELT()
23923 if (XType.bitsGT(AType)) { in foldSelectCCToShiftAnd()
23943 if (XType.bitsGT(AType)) { in foldSelectCCToShiftAnd()
H A DLegalizeDAG.cpp1744 if ((SrcVT.bitsGT(SlotVT) && in EmitStackConvert()
1764 if (SrcVT.bitsGT(SlotVT)) in EmitStackConvert()
H A DLegalizeVectorTypes.cpp1715 if (EltVT.bitsGT(Elt.getValueType())) in SplitVecRes_INSERT_VECTOR_ELT()
2280 if (Ops[I].getValueType().bitsGT(EltVT)) in SplitVecRes_VECTOR_SHUFFLE()
H A DTargetLowering.cpp224 if (VT.bitsGT(LVT)) in findOptimalMemOpLowering()
4506 if (Op0.getValueType().bitsGT(VT)) in SimplifySetCC()
H A DSelectionDAGBuilder.cpp737 if (BuiltVectorTy.getVectorElementType().bitsGT( in getCopyToPartsVector()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1538 return VT.bitsGT(MVT::i32) && Alignment >= Align(4); in allowsMisalignedMemoryAccesses()
1785 InVal = OpVT.bitsGT(InVal.getValueType()) ? in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2640 if (SVT.isInteger() && SVT.bitsGT(XLenVT)) { in lowerVECTOR_SHUFFLE()
2873 if (IndexVT.getScalarType().bitsGT(XLenVT)) { in lowerVECTOR_SHUFFLE()
5520 if (VecVT.bitsGT(getLMUL1VT(VecVT))) { in lowerINSERT_SUBVECTOR()
5549 if (VecVT.bitsGT(InterSubVT)) in lowerINSERT_SUBVECTOR()
5654 if (VecVT.bitsGT(getLMUL1VT(VecVT))) { in lowerEXTRACT_SUBVECTOR()
6553 if (XLenVT == MVT::i32 && IndexVT.getVectorElementType().bitsGT(XLenVT)) { in lowerMaskedGather()
6655 if (XLenVT == MVT::i32 && IndexVT.getVectorElementType().bitsGT(XLenVT)) { in lowerMaskedScatter()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4886 } else if (IdxVT.bitsGT(PtrVT)) in getRegForGEPIndex()
H A DAArch64ISelLowering.cpp4448 if (InVT.bitsGT(VT)) in getSVEPredicateBitCast()
7734 else if (SrcVT.bitsGT(VT)) in LowerFCOPYSIGN()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp6566 if (!LoadResultVT.bitsGT(TruncVT) || !TruncVT.isRound() || in optimizeLoadExt()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp15192 if (Op1VT.bitsGT(mVT)) { in PerformDAGCombine()