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Searched refs:addPred (Results 1 – 11 of 11) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DScheduleDAGInstrs.cpp274 UseSU->addPred(Dep); in addPhysRegDataDeps()
314 DefSU->addPred(Dep); in addPhysRegDeps()
440 UseSU->addPred(Dep); in addVRegDefDeps()
482 DefSU->addPred(Dep); in addVRegDefDeps()
527 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg)); in addVRegUseDeps()
543 SUb->addPred(Dep); in addChainDependency()
875 ExitSU.addPred(Dep); in buildSchedGraph()
1203 SuccSU->addPred(PredDep, /*Required=*/!PredDep.isArtificial()); in addEdge()
H A DMachinePipeliner.cpp788 SU.addPred(Dep); in addLoopCarriedDependences()
798 SU.addPred(Dep); in addLoopCarriedDependences()
806 SU.addPred(Dep); in addLoopCarriedDependences()
813 SU.addPred(Dep); in addLoopCarriedDependences()
822 SU.addPred(Dep); in addLoopCarriedDependences()
866 I.addPred(Dep); in updatePhiDependences()
887 I.addPred(Dep); in updatePhiDependences()
893 I.addPred(SDep(SU, SDep::Barrier)); in updatePhiDependences()
973 LastSU->addPred(Dep); in changeDependences()
1209 TargetSU->addPred(Dep); in swapAntiDependences()
[all …]
H A DScheduleDAG.cpp107 bool SUnit::addPred(const SDep &D, bool Required) { in addPred() function in SUnit
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h380 bool addPred(const SDep &D, bool Required = true);
389 return addPred(Dep); in addPredBarrier()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIMachineScheduler.h116 void addPred(SIScheduleBlock *Pred);
H A DSIMachineScheduler.cpp518 void SIScheduleBlock::addPred(SIScheduleBlock *Pred) { in addPred() function in SIScheduleBlock
1218 CurrentBlocks[SUID]->addPred(CurrentBlocks[Node2CurrentBlock[Pred->NodeNum]]); in createBlocksForVariant()
/llvm-project-15.0.7/llvm/lib/Transforms/ObjCARC/
H A DObjCARCOpts.cpp324 void addPred(BasicBlock *Pred) { Preds.push_back(Pred); } in addPred() function in __anonbfeb721b0111::BBState
1713 SuccStates.addPred(CurrBB); in ComputePostOrders()
1720 BBStates[SuccBB].addPred(CurrBB); in ComputePostOrders()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp437 S1.addPred(A, true); in apply()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp85 SU->addPred(D); in AddPred()
H A DScheduleDAGSDNodes.cpp513 if (!SU.addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) { in AddSchedEdges()
H A DScheduleDAGRRList.cpp227 SU->addPred(D); in AddPredQueued()
235 SU->addPred(D); in AddPred()