| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 758 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction() 759 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction() 767 TmpInst.addOperand(Inst.getOperand(2)); in ProcessInstruction() 768 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction() 769 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction() 777 TmpInst.addOperand(Inst.getOperand(2)); in ProcessInstruction() 778 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction() 779 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction() 801 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction() 802 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 559 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF() 565 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF() 580 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATIMMR6() 1033 MI.addOperand( in DecodeDEXT() 1035 MI.addOperand( in DecodeDEXT() 1076 MI.addOperand( in DecodeDINS() 1078 MI.addOperand( in DecodeDINS() 2462 MI.addOperand( in DecodeBgtzGroupBranchMMR6() 2466 MI.addOperand( in DecodeBgtzGroupBranchMMR6() 2507 MI.addOperand( in DecodeBlezGroupBranchMMR6() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/MCTargetDesc/ |
| H A D | CSKYMCCodeEmitter.cpp | 80 .addOperand(MI.getOperand(0)) in expandJBTF() 87 .addOperand(MI.getOperand(1)) in expandJBTF() 88 .addOperand(MI.getOperand(2)); in expandJBTF() 105 .addOperand(MI.getOperand(0)) in expandNEG() 106 .addOperand(MI.getOperand(1)); in expandNEG() 111 .addOperand(MI.getOperand(0)) in expandNEG() 112 .addOperand(MI.getOperand(0)) in expandNEG() 127 .addOperand(MI.getOperand(0)) in expandRSUBI() 128 .addOperand(MI.getOperand(1)); in expandRSUBI() 133 .addOperand(MI.getOperand(0)) in expandRSUBI() [all …]
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| H A D | CSKYAsmBackend.cpp | 302 Res.addOperand(Inst.getOperand(0)); in relaxInstruction() 303 Res.addOperand(Inst.getOperand(1)); in relaxInstruction() 307 Res.addOperand(Inst.getOperand(0)); in relaxInstruction() 311 Res.addOperand(Inst.getOperand(1)); in relaxInstruction() 315 Res.addOperand(Inst.getOperand(1)); in relaxInstruction() 320 Res.addOperand(Inst.getOperand(0)); in relaxInstruction() 321 Res.addOperand(Inst.getOperand(1)); in relaxInstruction() 322 Res.addOperand(Inst.getOperand(2)); in relaxInstruction() 326 Res.addOperand(Inst.getOperand(0)); in relaxInstruction() 327 Res.addOperand(Inst.getOperand(1)); in relaxInstruction() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2561 Inst.addOperand(MCOperand::createImm( in addRegShiftedRegOperands() 2572 Inst.addOperand(MCOperand::createImm( in addRegShiftedImmOperands() 5767 Inst.addOperand(Inst.getOperand(0)); in cvtThumbMultiply() 8718 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction() 8719 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction() 8720 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction() 8723 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction() 8724 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction() 8740 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction() 8741 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/Disassembler/ |
| H A D | AVRDisassembler.cpp | 74 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR8RegisterClass() 85 Inst.addOperand(MCOperand::createReg(Register)); in DecodeLD8RegisterClass() 138 Inst.addOperand(MCOperand::createImm(addr)); in decodeFIOARr() 154 Inst.addOperand(MCOperand::createImm(addr)); in decodeFIORdA() 162 Inst.addOperand(MCOperand::createImm(addr)); in decodeFIOBIT() 163 Inst.addOperand(MCOperand::createImm(b)); in decodeFIOBIT() 233 Inst.addOperand(MCOperand::createImm(k)); in decodeFWRdK() 260 Inst.addOperand( in decodeMemri() 334 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore() 344 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCompound.cpp | 216 CompoundInsn->addOperand(Rt); in getCompoundInsn() 228 CompoundInsn->addOperand(Rt); in getCompoundInsn() 229 CompoundInsn->addOperand(Rs); in getCompoundInsn() 242 CompoundInsn->addOperand(Rs); in getCompoundInsn() 243 CompoundInsn->addOperand(Rt); in getCompoundInsn() 255 CompoundInsn->addOperand(Rs); in getCompoundInsn() 256 CompoundInsn->addOperand(Rt); in getCompoundInsn() 268 CompoundInsn->addOperand(Rs); in getCompoundInsn() 269 CompoundInsn->addOperand(Rt); in getCompoundInsn() 286 CompoundInsn->addOperand(Rs); in getCompoundInsn() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonAsmPrinter.cpp | 252 T.addOperand(Inst.getOperand(i)); in ScaleVectorOffset() 284 Inst.addOperand(Reg); in HexagonProcessInstruction() 286 Inst.addOperand(S16); in HexagonProcessInstruction() 338 TmpInst.addOperand(Reg); in HexagonProcessInstruction() 355 TmpInst.addOperand(Reg); in HexagonProcessInstruction() 368 MappedInst.addOperand(Ps); in HexagonProcessInstruction() 446 TmpInst.addOperand( in HexagonProcessInstruction() 482 TmpInst.addOperand( in HexagonProcessInstruction() 509 TmpInst.addOperand( in HexagonProcessInstruction() 522 TmpInst.addOperand(Rdd); in HexagonProcessInstruction() [all …]
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| /llvm-project-15.0.7/llvm/include/llvm/MC/ |
| H A D | MCInstBuilder.h | 32 Inst.addOperand(MCOperand::createReg(Reg)); in addReg() 38 Inst.addOperand(MCOperand::createImm(Val)); in addImm() 44 Inst.addOperand(MCOperand::createSFPImm(Val)); in addSFPImm() 50 Inst.addOperand(MCOperand::createDFPImm(Val)); in addDFPImm() 56 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr() 62 Inst.addOperand(MCOperand::createInst(Val)); in addInst() 67 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand() function 68 Inst.addOperand(Op); in addOperand()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/Disassembler/ |
| H A D | PPCDisassembler.cpp | 76 Inst.addOperand(MCOperand::createImm(Offset)); in decodeDirectBrTarget() 87 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass() 204 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand() 222 Inst.addOperand(MCOperand::createImm(Imm)); in decodeImmZeroOperand() 267 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands() 289 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands() 305 Inst.addOperand(MCOperand::createImm(Disp)); in decodeMemRIHashOperands() 306 Inst.addOperand(MCOperand::createReg(RRegs[Base])); in decodeMemRIHashOperands() 366 Inst.addOperand(MCOperand::createImm(Disp << 3)); in decodeSPE8Operands() 382 Inst.addOperand(MCOperand::createImm(Disp << 2)); in decodeSPE4Operands() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEAsmPrinter.cpp | 87 SICInst.addOperand(RD); in emitSIC() 95 BSICInst.addOperand(R1); in emitBSIC() 96 BSICInst.addOperand(R2); in emitBSIC() 107 LEAInst.addOperand(RD); in emitLEAzzi() 111 LEAInst.addOperand(Imm); in emitLEAzzi() 131 LEAInst.addOperand(RD); in emitLEAzii() 134 LEAInst.addOperand(RS1); in emitLEAzii() 135 LEAInst.addOperand(Imm); in emitLEAzii() 156 Inst.addOperand(RD); in emitBinary() 157 Inst.addOperand(RS1); in emitBinary() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/Disassembler/ |
| H A D | SystemZDisassembler.cpp | 87 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass() 173 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand() 266 Inst.addOperand(MCOperand::createImm(Value)); in decodePCDBLOperand() 307 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDAddr12Operand() 328 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDXAddr12Operand() 352 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDLAddr12Len4Operand() 353 Inst.addOperand(MCOperand::createImm(Length + 1)); in decodeBDLAddr12Len4Operand() 364 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDLAddr12Len8Operand() 365 Inst.addOperand(MCOperand::createImm(Length + 1)); in decodeBDLAddr12Len8Operand() 376 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDRAddr12Operand() [all …]
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| /llvm-project-15.0.7/llvm/unittests/CodeGen/ |
| H A D | MachineInstrTest.cpp | 140 VD1VU->addOperand(*MF, in TEST() 142 VD1VU->addOperand(*MF, in TEST() 146 VD2VU->addOperand(*MF, in TEST() 148 VD2VU->addOperand(*MF, in TEST() 152 VD1SU->addOperand(*MF, in TEST() 154 VD1SU->addOperand(*MF, in TEST() 158 VD1SD->addOperand(*MF, in TEST() 160 VD1SD->addOperand(*MF, in TEST() 164 VD2PU->addOperand(*MF, in TEST() 166 VD2PU->addOperand(*MF, in TEST() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/Disassembler/ |
| H A D | CSKYDisassembler.cpp | 114 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodeGPRRegisterClass() 186 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodesGPRRegisterClass() 231 Inst.addOperand(MCOperand::createImm(Imm << S)); in decodeUImmOperand() 240 Inst.addOperand(MCOperand::createImm(Imm + 1)); in decodeOImmOperand() 248 Inst.addOperand(MCOperand::createImm((Imm & 0x7F) << 2)); in decodeLRW16Imm8() 251 Inst.addOperand(MCOperand::createImm(V << 2)); in decodeLRW16Imm8() 263 Inst.addOperand(MCOperand::createImm(16)); in decodeJMPIXImmOperand() 265 Inst.addOperand(MCOperand::createImm(24)); in decodeJMPIXImmOperand() 267 Inst.addOperand(MCOperand::createImm(32)); in decodeJMPIXImmOperand() 269 Inst.addOperand(MCOperand::createImm(40)); in decodeJMPIXImmOperand() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/Disassembler/ |
| H A D | RISCVDisassembler.cpp | 72 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass() 83 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR16RegisterClass() 94 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32RegisterClass() 105 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32CRegisterClass() 116 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64RegisterClass() 127 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64CRegisterClass() 158 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRCRegisterClass() 169 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRPF64RegisterClass() 180 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVRRegisterClass() 401 Inst.addOperand(Inst.getOperand(0)); in decodeRVCInstrRdRs1UImm() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 343 MI.addOperand(Imm4Op); in getInstruction() 641 Inst.addOperand( in DecodeMatrixTile() 776 Inst.addOperand(MCOperand::createImm(Imm)); in DecodeMRSSystemRegister() 786 Inst.addOperand(MCOperand::createImm(Imm)); in DecodeMSRSystemRegister() 809 Inst.addOperand(MCOperand::createImm(1)); in DecodeFMOVLaneInstruction() 980 Inst.addOperand(Inst.getOperand(0)); in DecodeMoveImmInstruction() 982 Inst.addOperand(MCOperand::createImm(imm)); in DecodeMoveImmInstruction() 1578 Inst.addOperand(MCOperand::createImm(imm)); in DecodeLogicalImmInstruction() 1595 Inst.addOperand(MCOperand::createImm(imm)); in DecodeModImmInstruction() 1633 Inst.addOperand(MCOperand::createImm(imm)); in DecodeModImmTiedInstruction() [all …]
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 101 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo, 132 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); in addImm() 137 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); in addCImm() 142 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); in addFPImm() 153 MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); in addFrameIndex() 198 MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask)); in addRegMask() 225 MI->addOperand(*MF, MO); in add() 231 MI->addOperand(*MF, MO); in add() 237 MI->addOperand(*MF, MachineOperand::CreateMetadata(MD)); in addMetadata() 253 MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID)); in addIntrinsicID() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/Disassembler/ |
| H A D | LanaiDisassembler.cpp | 127 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust() 170 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass() 180 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue() 182 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeRiMemoryValue() 193 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue() 195 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue() 206 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue() 208 Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset))); in decodeSplsValue() 225 MI.addOperand(MCOperand::createImm(Insn)); in decodeBranch() 233 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeShiftImm() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.cpp | 38 NopInst.addOperand(MCOperand::createImm(0)); in getNop() 39 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNop() 40 NopInst.addOperand(MCOperand::createReg(0)); in getNop() 43 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop() 44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop() 45 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNop() 46 NopInst.addOperand(MCOperand::createReg(0)); in getNop() 47 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
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| /llvm-project-15.0.7/bolt/lib/Target/X86/ |
| H A D | X86MCPlusBuilder.cpp | 1621 Inst.addOperand(TargetOp); in replaceMemOperandWithImm() 1624 Inst.addOperand(ImmOp); in replaceMemOperandWithImm() 1658 Inst.addOperand(TargetOp); in replaceMemOperandWithReg() 1659 Inst.addOperand(RegOp); in replaceMemOperandWithReg() 2506 IJmp.addOperand(TmpReg); in createIJmp32Frag() 2510 Load.addOperand(TmpReg); in createIJmp32Frag() 2511 Load.addOperand(BaseReg); in createIJmp32Frag() 2512 Load.addOperand(Scale); in createIJmp32Frag() 2513 Load.addOperand(IndexReg); in createIJmp32Frag() 2514 Load.addOperand(Offset); in createIJmp32Frag() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1693 Inst.addOperand(MCOperand::createImm(Op)); in DecodeSORegImmOperand() 2521 Inst.addOperand( in DecodeMemMultipleWritebackInstruction() 3682 Inst.addOperand(MCOperand::createImm(0)); in DecodeVLD3DupInstruction() 3816 Inst.addOperand(MCOperand::createReg(0)); in DecodeMVEModImmInstruction() 3817 Inst.addOperand(MCOperand::createImm(0)); in DecodeMVEModImmInstruction() 3843 Inst.addOperand(MCOperand::createImm(Qd)); in DecodeMVEVADCInstruction() 6155 Inst.addOperand(MCOperand::createImm(0)); in DecodeNEONComplexLane64Instruction() 6446 Inst.addOperand(MCOperand::createReg(0)); in DecodeVSCCLRM() 6703 Inst.addOperand(MCOperand::createReg(0)); in DecodeVSTRVLDR_SYSREG() 6964 Inst.addOperand(MCOperand::createReg(0)); in DecodeMVEVCMP() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/Disassembler/ |
| H A D | LoongArchDisassembler.cpp | 63 Inst.addOperand(MCOperand::createReg(LoongArch::R0 + RegNo)); in DecodeGPRRegisterClass() 72 Inst.addOperand(MCOperand::createReg(LoongArch::F0 + RegNo)); in DecodeFPR32RegisterClass() 81 Inst.addOperand(MCOperand::createReg(LoongArch::F0_64 + RegNo)); in DecodeFPR64RegisterClass() 90 Inst.addOperand(MCOperand::createReg(LoongArch::FCC0 + RegNo)); in DecodeCFRRegisterClass() 99 Inst.addOperand(MCOperand::createReg(LoongArch::FCSR0 + RegNo)); in DecodeFCSRRegisterClass() 108 Inst.addOperand(MCOperand::createImm(Imm + P)); in decodeUImmOperand() 119 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm) << S)); in decodeSImmOperand()
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| /llvm-project-15.0.7/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVAsmPrinter.cpp | 259 Inst.addOperand( in outputDebugSourceAndStrings() 270 Inst.addOperand(MCOperand::createReg(Reg)); in outputOpExtInstImports() 314 TmpInst.addOperand(MCOperand::createReg(Reg)); in outputEntryPoints() 372 Inst.addOperand(MCOperand::createReg(FuncReg)); in addOpsFromMDNode() 382 Inst.addOperand(MCOperand::createReg(Reg)); in outputExecutionModeFromMDNode() 383 Inst.addOperand(MCOperand::createImm(static_cast<unsigned>(EM))); in outputExecutionModeFromMDNode() 416 Inst.addOperand(MCOperand::createReg(FReg)); in outputExecutionMode() 418 Inst.addOperand(MCOperand::createImm(EM)); in outputExecutionMode() 420 Inst.addOperand(MCOperand::createImm(TypeCode)); in outputExecutionMode() 452 Inst.addOperand(MCOperand::createReg(Reg)); in outputAnnotations() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 538 NewInst.addOperand(I); in canonicalizeImmediates() 1228 TmpInst.addOperand(Rdd); in makeCombineInst() 1229 TmpInst.addOperand(MO1); in makeCombineInst() 1230 TmpInst.addOperand(MO2); in makeCombineInst() 1340 Inst.addOperand(Reg); in processInstruction() 1342 Inst.addOperand(S27); in processInstruction() 1628 TmpInst.addOperand(Rx); in processInstruction() 1629 TmpInst.addOperand(Rx); in processInstruction() 1630 TmpInst.addOperand(Rs); in processInstruction() 1648 TmpInst.addOperand(Rx); in processInstruction() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/Disassembler/ |
| H A D | ARCDisassembler.cpp | 140 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR32RegisterClass() 212 Inst.addOperand(MCOperand::createImm( in DecodeSignedOperand() 224 Inst.addOperand( in DecodeFromCyclicRange() 241 Inst.addOperand(MCOperand::createImm(LImm)); in DecodeStLImmInstruction() 242 Inst.addOperand(MCOperand::createImm(0)); in DecodeStLImmInstruction() 259 Inst.addOperand(MCOperand::createImm(LImm)); in DecodeLdLImmInstruction() 260 Inst.addOperand(MCOperand::createImm(0)); in DecodeLdLImmInstruction() 316 Inst.addOperand(MCOperand::createImm(U6Field)); in DecodeCCRU6Instruction() 318 Inst.addOperand(MCOperand::createImm(CCField)); in DecodeCCRU6Instruction() 329 Inst.addOperand(MCOperand::createImm(U6)); in DecodeSOPwithRU6() [all …]
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