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Searched refs:ZeroReg (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/Mips/
H A DTarget.cpp74 unsigned ZeroReg; in loadImmediate() local
77 ZeroReg = Mips::ZERO; in loadImmediate()
82 ZeroReg = Mips::ZERO_64; in loadImmediate()
91 .addReg(ZeroReg) in loadImmediate()
104 .addReg(ZeroReg) in loadImmediate()
123 .addReg(ZeroReg) in loadImmediate()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp114 Register ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
116 ZeroReg); in runOnMachineFunction()
122 .addReg(ZeroReg) in runOnMachineFunction()
H A DX86FrameLowering.cpp935 ZeroReg = InProlog ? X86::RCX in emitStackProbeInlineWindowsCoreCLR64() local
995 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg) in emitStackProbeInlineWindowsCoreCLR64()
996 .addReg(ZeroReg, RegState::Undef) in emitStackProbeInlineWindowsCoreCLR64()
997 .addReg(ZeroReg, RegState::Undef); in emitStackProbeInlineWindowsCoreCLR64()
1004 .addReg(ZeroReg) in emitStackProbeInlineWindowsCoreCLR64()
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/Mips/
H A DTargetTest.cpp46 const unsigned ZeroReg = IsGPR32 ? Mips::ZERO : Mips::ZERO_64; in IsLoadLow16BitImm() local
49 ElementsAre(IsReg(Reg), IsReg(ZeroReg), IsImm(Value))); in IsLoadLow16BitImm()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DRelocation.txt56 Register ZeroReg, RegisterOperand GPROpnd> {
59 def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
H A DMipsSEInstrInfo.cpp87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
182 if (ZeroReg) in copyPhysReg()
183 MIB.addReg(ZeroReg); in copyPhysReg()
H A DMipsSEISelDAGToDAG.cpp85 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
93 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
99 ZeroReg = Mips::ZERO_64; in replaceUsesWithZeroReg()
119 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) in replaceUsesWithZeroReg()
122 MO.setReg(ZeroReg); in replaceUsesWithZeroReg()
H A DMipsAsmPrinter.cpp140 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch() local
141 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); in emitPseudoIndirectBranch()
H A DMipsInstrInfo.td3173 Register ZeroReg, RegisterOperand GPROpnd> {
3181 (Addiu ZeroReg, tglobaladdr:$in)>;
3183 (Addiu ZeroReg, tblockaddress:$in)>;
3185 (Addiu ZeroReg, tjumptable:$in)>;
3187 (Addiu ZeroReg, tconstpool:$in)>;
3189 (Addiu ZeroReg, tglobaltlsaddr:$in)>;
3191 (Addiu ZeroReg, texternalsym:$in)>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp550 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
551 putConstant(I, ZeroReg, 0); in selectCmp()
556 ZeroReg)) in selectCmp()
562 RHSReg, ZeroReg)) in selectCmp()
H A DARMFastISel.cpp1476 unsigned ZeroReg = fastMaterializeConstant(Zero); in SelectCmp() local
1479 .addReg(ZeroReg).addImm(1) in SelectCmp()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3431 MIB.addReg(ZeroReg); in copyGPRRegTuple()
5804 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
5811 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
5828 .addReg(ZeroReg) in genAlternativeCodeSequence()
5843 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
5847 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
5853 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
5861 .addReg(ZeroReg) in genAlternativeCodeSequence()
5896 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
5903 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
[all …]
H A DAArch64InstrInfo.h176 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
H A DAArch64ExpandPseudoInsts.cpp76 unsigned ExtendImm, unsigned ZeroReg,
186 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP() argument
219 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
H A DAArch64ISelDAGToDAG.cpp2927 unsigned ZeroReg; in tryShiftAmountMod() local
2931 ZeroReg = AArch64::WZR; in tryShiftAmountMod()
2935 ZeroReg = AArch64::XZR; in tryShiftAmountMod()
2938 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT); in tryShiftAmountMod()
2947 unsigned ZeroReg; in tryShiftAmountMod() local
2951 ZeroReg = AArch64::WZR; in tryShiftAmountMod()
2955 ZeroReg = AArch64::XZR; in tryShiftAmountMod()
2958 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT); in tryShiftAmountMod()
H A DAArch64FastISel.cpp380 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt() local
383 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
4857 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv() local
4860 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, SelectReg, in selectSDiv()
H A DAArch64ISelLowering.cpp17070 unsigned ZeroReg; in replaceZeroVectorStore() local
17073 ZeroReg = AArch64::WZR; in replaceZeroVectorStore()
17076 ZeroReg = AArch64::XZR; in replaceZeroVectorStore()
17080 DAG.getCopyFromReg(DAG.getEntryNode(), DL, ZeroReg, ZeroVT); in replaceZeroVectorStore()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DInstructionSelectorImpl.h892 int64_t ZeroReg = MatchTable[CurrentIdx++]; in executeMatchTable() local
896 OutMIs[NewInsnID].addReg(ZeroReg); in executeMatchTable()
902 << OpIdx << ", " << ZeroReg << ")\n"); in executeMatchTable()
/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2741 SrcReg = ZeroReg; in loadImmediate()
4189 unsigned ZeroReg; in expandDivRem() local
4194 ZeroReg = Mips::ZERO_64; in expandDivRem()
4198 ZeroReg = Mips::ZERO; in expandDivRem()
4222 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4229 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); in expandDivRem()
4235 TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI); in expandDivRem()
4254 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4274 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4302 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI); in expandDivRem()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVInstructionSelector.cpp930 Register ZeroReg = buildZerosVal(ResType, I); in selectSelect() local
941 .addUse(ZeroReg) in selectSelect()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1887 Register ZeroReg; in applyCombineUnmergeZExtToZExt() local
1889 if (!ZeroReg) in applyCombineUnmergeZExtToZExt()
1890 ZeroReg = Builder.buildConstant(Dst0Ty, 0).getReg(0); in applyCombineUnmergeZExtToZExt()
1891 replaceRegWith(MRI, MI.getOperand(Idx).getReg(), ZeroReg); in applyCombineUnmergeZExtToZExt()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2116 MCRegister ZeroReg; in onlyFoldImmediate() local
2119 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2121 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in onlyFoldImmediate()
2125 UseMI.getOperand(UseIdx).setReg(ZeroReg); in onlyFoldImmediate()
H A DPPCISelLowering.cpp11578 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitPartwordAtomicBinary() local
11645 if (ptrA != ZeroReg) { in EmitPartwordAtomicBinary()
11690 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
11734 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
12626 Register ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitInstrWithCustomInserter() local
12659 if (ptrA != ZeroReg) { in EmitInstrWithCustomInserter()
12716 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
12740 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
12753 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
H A DPPCISelDAGToDAG.cpp6002 SDValue ZeroReg = in Select() local
6025 Subtarget->isLittleEndian() ? PPC::LVSR : PPC::LVSL, dl, Type, ZeroReg, in Select()
6030 {ZeroReg, N->getOperand(1), N->getOperand(0)}); in Select()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp7587 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion() local
7589 ZeroReg, 0); in convertNonUniformLoopRegion()
7590 HeaderPHIBuilder.addReg(ZeroReg); in convertNonUniformLoopRegion()