Lines Matching refs:ZeroReg
3416 unsigned Opcode, unsigned ZeroReg, in copyGPRRegTuple() argument
3431 MIB.addReg(ZeroReg); in copyGPRRegTuple()
4846 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
4865 if (MI->getOperand(3).getReg() != ZeroReg) in canCombine()
4879 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
4880 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
4940 auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, in getMaddPatterns()
4942 if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) { in getMaddPatterns()
5799 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
5804 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
5811 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
5828 .addReg(ZeroReg) in genAlternativeCodeSequence()
5843 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
5847 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
5853 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
5861 .addReg(ZeroReg) in genAlternativeCodeSequence()
5891 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
5896 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
5903 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
5919 .addReg(ZeroReg) in genAlternativeCodeSequence()