Home
last modified time | relevance | path

Searched refs:VReg (Results 1 – 25 of 101) sorted by relevance

12345

/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegNumbering.cpp92 Register VReg = Register::index2VirtReg(VRegIdx); in runOnMachineFunction() local
94 if (MRI.use_empty(VReg)) in runOnMachineFunction()
97 if (MFI.isVRegStackified(VReg)) { in runOnMachineFunction()
98 LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg " in runOnMachineFunction()
100 MFI.setWAReg(VReg, INT32_MIN | NumStackRegs++); in runOnMachineFunction()
103 if (MFI.getWAReg(VReg) == WebAssemblyFunctionInfo::UnusedReg) { in runOnMachineFunction()
104 LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg " << CurReg << "\n"); in runOnMachineFunction()
105 MFI.setWAReg(VReg, CurReg++); in runOnMachineFunction()
H A DWebAssemblyReplacePhysRegs.cpp84 unsigned VReg = WebAssembly::NoRegister; in runOnMachineFunction() local
88 if (VReg == WebAssembly::NoRegister) { in runOnMachineFunction()
89 VReg = MRI.createVirtualRegister(RC); in runOnMachineFunction()
93 FI->setFrameBaseVreg(VReg); in runOnMachineFunction()
95 dbgs() << "replacing preg " << PReg << " with " << VReg << " (" in runOnMachineFunction()
96 << Register::virtReg2Index(VReg) << ")\n"; in runOnMachineFunction()
100 MO.setReg(VReg); in runOnMachineFunction()
H A DWebAssemblyMachineFunctionInfo.h129 void stackifyVReg(MachineRegisterInfo &MRI, unsigned VReg) { in stackifyVReg() argument
130 assert(MRI.getUniqueVRegDef(VReg)); in stackifyVReg()
131 auto I = Register::virtReg2Index(VReg); in stackifyVReg()
136 void unstackifyVReg(unsigned VReg) { in unstackifyVReg() argument
137 auto I = Register::virtReg2Index(VReg); in unstackifyVReg()
141 bool isVRegStackified(unsigned VReg) const { in isVRegStackified() argument
142 auto I = Register::virtReg2Index(VReg); in isVRegStackified()
149 void setWAReg(unsigned VReg, unsigned WAReg) { in setWAReg() argument
151 auto I = Register::virtReg2Index(VReg); in setWAReg()
155 unsigned getWAReg(unsigned VReg) const { in getWAReg() argument
[all …]
H A DWebAssemblyRegColoring.cpp67 unsigned VReg) { in computeWeight() argument
69 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg)) in computeWeight()
101 Register VReg = Register::index2VirtReg(I); in runOnMachineFunction() local
102 if (MFI.isVRegStackified(VReg)) in runOnMachineFunction()
105 if (MRI->use_empty(VReg)) in runOnMachineFunction()
108 LiveInterval *LI = &Liveness->getInterval(VReg); in runOnMachineFunction()
110 LI->setWeight(computeWeight(MRI, MBFI, VReg)); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DSwiftErrorValueTracking.cpp38 VRegDefMap[Key] = VReg; in getOrCreateVReg()
39 VRegUpwardsUse[Key] = VReg; in getOrCreateVReg()
40 return VReg; in getOrCreateVReg()
47 VRegDefMap[std::make_pair(MBB, Val)] = VReg; in setCurrentVReg()
60 VRegDefUses[Key] = VReg; in getOrCreateVRegDefAt()
61 setCurrentVReg(MBB, Val, VReg); in getOrCreateVRegDefAt()
62 return VReg; in getOrCreateVRegDefAt()
72 Register VReg = getOrCreateVReg(MBB, Val); in getOrCreateVRegUseAt() local
73 VRegDefUses[Key] = VReg; in getOrCreateVRegUseAt()
74 return VReg; in getOrCreateVRegUseAt()
[all …]
H A DMIRVRegNamerUtils.cpp49 for (const auto &VReg : VRegs) { in getVRegRenameMap() local
50 const unsigned Reg = VReg.getReg(); in getVRegRenameMap()
51 VRM[Reg] = createVirtualRegisterWithLowerName(Reg, GetUniqueVRegName(VReg)); in getVRegRenameMap()
138 unsigned VRegRenamer::createVirtualRegister(unsigned VReg) { in createVirtualRegister() argument
139 assert(Register::isVirtualRegister(VReg) && "Expected Virtual Registers"); in createVirtualRegister()
140 std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg)); in createVirtualRegister()
141 return createVirtualRegisterWithLowerName(VReg, Name); in createVirtualRegister()
165 unsigned VRegRenamer::createVirtualRegisterWithLowerName(unsigned VReg, in createVirtualRegisterWithLowerName() argument
168 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); in createVirtualRegisterWithLowerName()
170 : MRI.createGenericVirtualRegister(MRI.getType(VReg), LowerName); in createVirtualRegisterWithLowerName()
H A DLiveRangeEdit.cpp37 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createEmptyIntervalFrom()
39 LiveInterval &LI = LIS.createEmptyInterval(VReg); in createEmptyIntervalFrom()
57 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createFrom()
66 LIS.getInterval(VReg).markNotSpillable(); in createFrom()
67 return VReg; in createFrom()
442 unsigned VReg = LI->reg(); in eliminateDeadDefs() local
444 TheDelegate->LRE_WillShrinkVirtReg(VReg); in eliminateDeadDefs()
452 if (llvm::is_contained(RegsBeingSpilled, VReg)) in eliminateDeadDefs()
467 if (Original != VReg && Original != 0) in eliminateDeadDefs()
478 LiveRangeEdit::MRI_NoteNewVirtualRegister(Register VReg) { in MRI_NoteNewVirtualRegister() argument
[all …]
H A DRegAllocPBQP.cpp334 LiveInterval &LI = LIS.getInterval(VReg); in apply()
604 Register VReg = Worklist.back(); in initializeGraph() local
663 auto VReg = KV.first; in initializeGraph() local
666 if (LIS.getInterval(VReg).empty()) { in initializeGraph()
667 EmptyIntervalVRegs.insert(VReg); in initializeGraph()
668 VRegsToAlloc.erase(VReg); in initializeGraph()
683 G.getNodeMetadata(NId).setVReg(VReg); in initializeGraph()
686 G.getMetadata().setNodeIdForVReg(VReg, NId); in initializeGraph()
690 void RegAllocPBQP::spillVReg(Register VReg, in spillVReg() argument
694 VRegsToAlloc.erase(VReg); in spillVReg()
[all …]
H A DLiveIntervalUnion.cpp160 const LiveInterval *VReg = LiveUnionI.value(); in collectInterferingVRegs() local
161 if (VReg != RecentReg && !isSeenInterference(VReg)) { in collectInterferingVRegs()
162 RecentReg = VReg; in collectInterferingVRegs()
163 InterferingVRegs.push_back(VReg); in collectInterferingVRegs()
H A DMachineRegisterInfo.cpp170 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg, in cloneVirtualRegister() argument
173 VRegInfo[Reg].first = VRegInfo[VReg].first; in cloneVirtualRegister()
174 setType(Reg, getType(VReg)); in cloneVirtualRegister()
180 void MachineRegisterInfo::setType(Register VReg, LLT Ty) { in setType() argument
181 VRegToType.grow(VReg); in setType()
182 VRegToType[VReg] = Ty; in setType()
441 MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const { in getLiveInPhysReg()
443 if (LI.second == VReg) in getLiveInPhysReg()
H A DMIRVRegNamerUtils.h73 unsigned createVirtualRegister(unsigned VReg);
76 unsigned createVirtualRegisterWithLowerName(unsigned VReg, StringRef Name);
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h747 void setType(Register VReg, LLT Ty);
774 assert(VReg.isVirtual()); in setRegAllocationHint()
775 RegAllocHints[VReg].first = Type; in setRegAllocationHint()
776 RegAllocHints[VReg].second.clear(); in setRegAllocationHint()
793 void clearSimpleHint(Register VReg) { in clearSimpleHint() argument
794 assert (!RegAllocHints[VReg].first && in clearSimpleHint()
796 RegAllocHints[VReg].second.clear(); in clearSimpleHint()
804 assert(VReg.isVirtual()); in getRegAllocationHint()
814 assert(VReg.isVirtual()); in getSimpleHint()
823 assert(VReg.isVirtual()); in getRegAllocationHints()
[all …]
H A DRegAllocPBQP.h148 void setNodeIdForVReg(Register VReg, GraphBase::NodeId NId) { in setNodeIdForVReg() argument
149 VRegToNodeId[VReg.id()] = NId; in setNodeIdForVReg()
152 GraphBase::NodeId getNodeIdForVReg(Register VReg) const { in getNodeIdForVReg() argument
153 auto VRegItr = VRegToNodeId.find(VReg); in getNodeIdForVReg()
187 OptUnsafeEdges(new unsigned[NumOpts]), VReg(Other.VReg), in NodeMetadata()
203 void setVReg(Register VReg) { this->VReg = VReg; } in setVReg() argument
204 Register getVReg() const { return VReg; } in getVReg()
262 Register VReg; variable
H A DScheduleDAGInstrs.h57 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) in VReg2SUnit()
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} in VReg2SUnit()
69 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, in VReg2SUnitOperIdx()
71 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {} in VReg2SUnitOperIdx()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.h102 const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder,
105 SPIRVType *assignIntTypeToVReg(unsigned BitWidth, Register VReg,
108 Register VReg, MachineInstr &I,
113 void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg,
134 SPIRVType *getSPIRVTypeForVReg(Register VReg) const;
137 bool hasSPIRVTypeForVReg(Register VReg) const { in hasSPIRVTypeForVReg() argument
138 return getSPIRVTypeForVReg(VReg) != nullptr; in hasSPIRVTypeForVReg()
148 bool isScalarOfType(Register VReg, unsigned TypeOpcode) const;
153 bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const;
162 SPIRV::StorageClass getPointerStorageClass(Register VReg) const;
H A DSPIRVGlobalRegistry.cpp28 Register VReg, in assignIntTypeToVReg() argument
32 assignSPIRVTypeToVReg(SpirvType, VReg, *CurMF); in assignIntTypeToVReg()
41 assignSPIRVTypeToVReg(SpirvType, VReg, *CurMF); in assignVectTypeToVReg()
51 assignSPIRVTypeToVReg(SpirvType, VReg, MIRBuilder.getMF()); in assignTypeToVReg()
56 Register VReg, in assignSPIRVTypeToVReg() argument
58 VRegToTypeMap[&MF][VReg] = SpirvType; in assignSPIRVTypeToVReg()
601 auto tt = t->second.find(VReg); in getSPIRVTypeForVReg()
631 bool SPIRVGlobalRegistry::isScalarOfType(Register VReg, in isScalarOfType() argument
633 SPIRVType *Type = getSPIRVTypeForVReg(VReg); in isScalarOfType()
640 SPIRVType *Type = getSPIRVTypeForVReg(VReg); in isScalarOrVectorOfType()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp289 VReg, MRI, /*LookThroughInstrs*/ false); in getIConstantVRegVal()
290 assert((!ValAndVReg || ValAndVReg->VReg == VReg) && in getIConstantVRegVal()
299 Optional<APInt> Val = getIConstantVRegVal(VReg, MRI); in getIConstantVRegSExtVal()
330 VReg = MI->getOperand(1).getReg(); in getConstantVRegValWithLookThrough()
333 VReg = MI->getOperand(1).getReg(); in getConstantVRegValWithLookThrough()
334 if (Register::isPhysicalRegister(VReg)) in getConstantVRegValWithLookThrough()
338 VReg = MI->getOperand(1).getReg(); in getConstantVRegValWithLookThrough()
367 return ValueAndVReg{Val, VReg}; in getConstantVRegValWithLookThrough()
428 Reg->VReg}; in getFConstantVRegValWithLookThrough()
433 MachineInstr *MI = MRI.getVRegDef(VReg); in getConstantFPVRegVal()
[all …]
H A DInstructionSelect.cpp250 unsigned VReg = Register::index2VirtReg(I); in runOnMachineFunction() local
253 if (!MRI.def_empty(VReg)) in runOnMachineFunction()
254 MI = &*MRI.def_instr_begin(VReg); in runOnMachineFunction()
255 else if (!MRI.use_empty(VReg)) { in runOnMachineFunction()
256 MI = &*MRI.use_instr_begin(VReg); in runOnMachineFunction()
264 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); in runOnMachineFunction()
271 const LLT Ty = MRI.getType(VReg); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h169 Optional<APInt> getIConstantVRegVal(Register VReg,
173 Optional<int64_t> getIConstantVRegSExtVal(Register VReg,
180 Register VReg; member
186 getIConstantVRegValWithLookThrough(Register VReg,
193 Register VReg, const MachineRegisterInfo &MRI,
198 Register VReg; member
204 getFConstantVRegValWithLookThrough(Register VReg,
208 const ConstantFP* getConstantFPVRegVal(Register VReg,
395 Optional<FPValueAndVReg> getFConstantSplat(Register VReg,
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp281 return VReg; in getVR()
335 VReg = NewVReg; in AddRegisterOperand()
386 Register VReg = R->getReg(); in AddOperand() local
402 VReg = NewVReg; in AddOperand()
462 return VReg; in ConstrainForSubReg()
470 .addReg(VReg); in ConstrainForSubReg()
620 NewVReg).addReg(VReg); in EmitCopyToRegClassNode()
799 MIB.addReg(VReg); in EmitDbgInstrRef()
808 unsigned VReg; in EmitDbgInstrRef() local
815 if (!MRI->hasOneDef(VReg)) in EmitDbgInstrRef()
[all …]
H A DSDNodeDbgValue.h68 return u.VReg; in getVReg()
77 static SDDbgOperand fromVReg(unsigned VReg) { in fromVReg() argument
78 return SDDbgOperand(VReg, VREG); in fromVReg()
110 unsigned VReg; ///< Valid for registers. member
125 u.VReg = VRegOrFrameIdx; in SDDbgOperand()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.h248 void addLiveInAttr(Register VReg, ISD::ArgFlagsTy Flags) { in addLiveInAttr() argument
249 LiveInAttrs.push_back(std::make_pair(VReg, Flags)); in addLiveInAttr()
254 bool isLiveInSExt(Register VReg) const;
258 bool isLiveInZExt(Register VReg) const;
H A DPPCMachineFunctionInfo.cpp61 bool PPCFunctionInfo::isLiveInSExt(Register VReg) const { in isLiveInSExt()
63 if (LiveIn.first == VReg) in isLiveInSExt()
68 bool PPCFunctionInfo::isLiveInZExt(Register VReg) const { in isLiveInZExt()
70 if (LiveIn.first == VReg) in isLiveInZExt()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td74 class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,
75 VReg f2regclass, VReg f4regclass, VReg f8regclass, string mx> {
77 VReg vrclass = regclass;
78 VReg wvrclass = wregclass;
170 VReg RC = !cast<VReg>("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX,
187 VReg RegClass = Reg;
784 class VPseudoILoadNoMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
817 class VPseudoILoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
998 class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
1114 class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp590 return error(VReg.ID.SourceRange.Start, in parseRegisterInfo()
592 Twine(VReg.ID.Value) + "'"); in parseRegisterInfo()
595 if (StringRef(VReg.Class.Value).equals("_")) { in parseRegisterInfo()
607 VReg.Class.SourceRange.Start, in parseRegisterInfo()
609 VReg.Class.Value + "'"); in parseRegisterInfo()
615 if (!VReg.PreferredRegister.Value.empty()) { in parseRegisterInfo()
617 return error(VReg.Class.SourceRange.Start, in parseRegisterInfo()
631 Register VReg; in parseRegisterInfo() local
637 VReg = Info->VReg; in parseRegisterInfo()
639 RegInfo.addLiveIn(Reg, VReg); in parseRegisterInfo()
[all …]

12345