Lines Matching refs:VReg

278     Register VReg = MRI->createVirtualRegister(RC);  in getVR()  local
280 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
281 return VReg; in getVR()
304 Register VReg = getVR(Op, VRBaseMap); in AddRegisterOperand() local
328 = MRI->constrainRegClass(VReg, OpRC, MinNumRegs); in AddRegisterOperand()
334 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddRegisterOperand()
335 VReg = NewVReg; in AddRegisterOperand()
365 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
386 Register VReg = R->getReg(); in AddOperand() local
398 if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) { in AddOperand()
401 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddOperand()
402 VReg = NewVReg; in AddOperand()
408 MIB.addReg(VReg, getImplRegState(Imp)); in AddOperand()
450 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx, in ConstrainForSubReg() argument
452 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg()
458 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); in ConstrainForSubReg()
462 return VReg; in ConstrainForSubReg()
470 .addReg(VReg); in ConstrainForSubReg()
612 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); in EmitCopyToRegClassNode() local
620 NewVReg).addReg(VReg); in EmitCopyToRegClassNode()
797 auto EmitHalfDoneInstrRef = [&](unsigned VReg) -> MachineInstr * { in EmitDbgInstrRef() argument
799 MIB.addReg(VReg); in EmitDbgInstrRef()
808 unsigned VReg; in EmitDbgInstrRef() local
811 VReg = DbgOperand.getVReg(); in EmitDbgInstrRef()
815 if (!MRI->hasOneDef(VReg)) in EmitDbgInstrRef()
816 return EmitHalfDoneInstrRef(VReg); in EmitDbgInstrRef()
818 DefMI = &*MRI->def_instr_begin(VReg); in EmitDbgInstrRef()
830 VReg = getVR(Op, VRBaseMap); in EmitDbgInstrRef()
834 if (!MRI->hasOneDef(VReg)) in EmitDbgInstrRef()
835 return EmitHalfDoneInstrRef(VReg); in EmitDbgInstrRef()
837 DefMI = &*MRI->def_instr_begin(VReg); in EmitDbgInstrRef()
844 return EmitHalfDoneInstrRef(VReg); in EmitDbgInstrRef()
851 if (MO.isReg() && MO.isDef() && MO.getReg() == VReg) in EmitDbgInstrRef()