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Searched refs:VECTOR_SPLICE (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dnamed-vector-shuffles-neon.ll7 ; VECTOR_SPLICE (index)
66 ; VECTOR_SPLICE (trailing elements)
H A Dnamed-vector-shuffles-sve.ll7 ; VECTOR_SPLICE (index)
381 ; VECTOR_SPLICE (trailing elements)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h598 VECTOR_SPLICE, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp297 case ISD::VECTOR_SPLICE: return "vector_splice"; in getOperationName()
H A DLegalizeDAG.cpp3109 case ISD::VECTOR_SPLICE: { in ExpandNode()
4659 case ISD::VECTOR_SPLICE: { in PromoteNode()
4662 Tmp3 = DAG.getNode(ISD::VECTOR_SPLICE, dl, NVT, Tmp1, Tmp2, in PromoteNode()
H A DLegalizeIntegerTypes.cpp116 case ISD::VECTOR_SPLICE: in PromoteIntegerResult()
5169 return DAG.getNode(ISD::VECTOR_SPLICE, dl, OutVT, V0, V1, N->getOperand(2)); in PromoteIntRes_VECTOR_SPLICE()
H A DLegalizeVectorTypes.cpp995 case ISD::VECTOR_SPLICE: in SplitVectorResult()
H A DTargetLowering.cpp9632 assert(Node->getOpcode() == ISD::VECTOR_SPLICE && "Unexpected opcode!"); in expandVectorSplice()
H A DSelectionDAG.cpp6453 case ISD::VECTOR_SPLICE: { in getNode()
H A DSelectionDAGBuilder.cpp11341 setValue(&I, DAG.getNode(ISD::VECTOR_SPLICE, DL, VT, V1, V2, in visitVectorSplice()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp870 setOperationAction(ISD::VECTOR_SPLICE, VT, Expand); in initActions()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp887 ISD::VECTOR_SPLICE, ISD::SIGN_EXTEND_INREG, in AArch64TargetLowering()
1165 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in AArch64TargetLowering()
1321 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in AArch64TargetLowering()
1435 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv2i1, MVT::nxv2i64); in AArch64TargetLowering()
1436 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv4i1, MVT::nxv4i32); in AArch64TargetLowering()
1437 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv8i1, MVT::nxv8i16); in AArch64TargetLowering()
1438 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv16i1, MVT::nxv16i8); in AArch64TargetLowering()
1686 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in addTypeForFixedLengthSVE()
5611 case ISD::VECTOR_SPLICE: in LowerOperation()
11652 SDValue Splice = DAG.getNode(ISD::VECTOR_SPLICE, DL, ContainerVT, NewInVec, in LowerEXTRACT_SUBVECTOR()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp536 ISD::VECTOR_SPLICE, VT, in RISCVTargetLowering()
618 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in RISCVTargetLowering()
704 setOperationAction({ISD::VECTOR_REVERSE, ISD::VECTOR_SPLICE}, VT, Custom); in RISCVTargetLowering()
3464 case ISD::VECTOR_SPLICE: in LowerOperation()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td686 def vector_splice : SDNode<"ISD::VECTOR_SPLICE", SDTVecSlice, []>;