Lines Matching refs:VECTOR_SPLICE
887 ISD::VECTOR_SPLICE, ISD::SIGN_EXTEND_INREG, in AArch64TargetLowering()
1165 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in AArch64TargetLowering()
1321 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in AArch64TargetLowering()
1435 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv2i1, MVT::nxv2i64); in AArch64TargetLowering()
1436 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv4i1, MVT::nxv4i32); in AArch64TargetLowering()
1437 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv8i1, MVT::nxv8i16); in AArch64TargetLowering()
1438 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv16i1, MVT::nxv16i8); in AArch64TargetLowering()
1686 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in addTypeForFixedLengthSVE()
5611 case ISD::VECTOR_SPLICE: in LowerOperation()
11652 SDValue Splice = DAG.getNode(ISD::VECTOR_SPLICE, DL, ContainerVT, NewInVec, in LowerEXTRACT_SUBVECTOR()
19395 SDValue Splice = DAG.getNode(ISD::VECTOR_SPLICE, DL, ExtIntTy, LHS, RHS, Idx); in performSVESpliceCombine()
19569 case ISD::VECTOR_SPLICE: in PerformDAGCombine()