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Searched refs:VE (Results 1 – 25 of 95) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp93 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
94 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
95 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
96 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
99 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7,
100 VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15,
101 VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23,
102 VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31,
103 VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39,
104 VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47,
[all …]
/llvm-project-15.0.7/llvm/lib/Target/VE/MCTargetDesc/
H A DVEAsmBackend.cpp36 case VE::fixup_ve_hi32: in adjustFixupValue()
37 case VE::fixup_ve_pc_hi32: in adjustFixupValue()
38 case VE::fixup_ve_got_hi32: in adjustFixupValue()
40 case VE::fixup_ve_plt_hi32: in adjustFixupValue()
44 case VE::fixup_ve_reflong: in adjustFixupValue()
45 case VE::fixup_ve_srel32: in adjustFixupValue()
46 case VE::fixup_ve_lo32: in adjustFixupValue()
47 case VE::fixup_ve_pc_lo32: in adjustFixupValue()
72 case VE::fixup_ve_srel32: in getFixupKindNumBytes()
73 case VE::fixup_ve_hi32: in getFixupKindNumBytes()
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H A DVEELFObjectWriter.cpp70 case VE::fixup_ve_reflong: in getRelocType()
71 case VE::fixup_ve_srel32: in getRelocType()
94 case VE::fixup_ve_reflong: in getRelocType()
96 case VE::fixup_ve_srel32: in getRelocType()
100 case VE::fixup_ve_hi32: in getRelocType()
102 case VE::fixup_ve_lo32: in getRelocType()
104 case VE::fixup_ve_pc_hi32: in getRelocType()
108 case VE::fixup_ve_pc_lo32: in getRelocType()
112 case VE::fixup_ve_got_hi32: in getRelocType()
114 case VE::fixup_ve_got_lo32: in getRelocType()
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H A DVEMCExpr.cpp144 return VE::fixup_ve_reflong; in getFixupKind()
146 return VE::fixup_ve_hi32; in getFixupKind()
148 return VE::fixup_ve_lo32; in getFixupKind()
150 return VE::fixup_ve_pc_hi32; in getFixupKind()
152 return VE::fixup_ve_pc_lo32; in getFixupKind()
154 return VE::fixup_ve_got_hi32; in getFixupKind()
156 return VE::fixup_ve_got_lo32; in getFixupKind()
162 return VE::fixup_ve_plt_hi32; in getFixupKind()
164 return VE::fixup_ve_plt_lo32; in getFixupKind()
170 return VE::fixup_ve_tpoff_hi32; in getFixupKind()
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H A DVEMCExpr.h68 VE::Fixups getFixupKind() const { return getFixupKind(Kind); } in getFixupKind()
90 static VE::Fixups getFixupKind(VariantKind Kind);
H A DVEMCTargetDesc.cpp39 unsigned Reg = MRI.getDwarfRegNum(VE::SX11, true); in createVEMCAsmInfo()
53 InitVEMCRegisterInfo(X, VE::SX10); in createVEMCRegisterInfo()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp200 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX17) in emitEpilogueInsns()
205 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX16) in emitEpilogueInsns()
209 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX15) in emitEpilogueInsns()
215 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX10) in emitEpilogueInsns()
219 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX9) in emitEpilogueInsns()
243 BuildMI(MBB, MBBI, DL, TII.get(VE::LEArii), VE::SX11) in emitSPAdjustment()
257 BuildMI(MBB, MBBI, DL, TII.get(VE::ANDrm), VE::SX13) in emitSPAdjustment()
268 BuildMI(MBB, MBBI, DL, TII.get(VE::ANDrm), VE::SX11) in emitSPAdjustment()
354 BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX9) in emitPrologue()
367 BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX17) in emitPrologue()
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H A DVEInstrInfo.cpp774 return (reg - VE::VMP0) * 2 + VE::VM0; in getVM512Upper()
845 {VE::VFMKyal, {VE::VFMKLal, VE::VFMKLal}}, in expandPseudoVFMK()
846 {VE::VFMKynal, {VE::VFMKLnal, VE::VFMKLnal}}, in expandPseudoVFMK()
847 {VE::VFMKWyvl, {VE::PVFMKWUPvl, VE::PVFMKWLOvl}}, in expandPseudoVFMK()
848 {VE::VFMKWyvyl, {VE::PVFMKWUPvml, VE::PVFMKWLOvml}}, in expandPseudoVFMK()
849 {VE::VFMKSyvl, {VE::PVFMKSUPvl, VE::PVFMKSLOvl}}, in expandPseudoVFMK()
850 {VE::VFMKSyvyl, {VE::PVFMKSUPvml, VE::PVFMKSLOvml}}, in expandPseudoVFMK()
1046 BuildMI(BB, dl, TII.get(VE::LDrii), VE::SX61) in expandExtendStackPseudo()
1050 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX62) in expandExtendStackPseudo()
1053 BuildMI(BB, dl, TII.get(VE::LEAzii), VE::SX63) in expandExtendStackPseudo()
[all …]
H A DVERegisterInfo.cpp93 Reserved.set(VE::VM0); in getReservedRegs()
94 Reserved.set(VE::VMP0); in getReservedRegs()
101 case VE::VM0: in isConstantPhysReg()
102 case VE::VMP0: in isConstantPhysReg()
466 case VE::STQrii: in processMI()
469 case VE::LDQrii: in processMI()
472 case VE::STVMrii: in processMI()
475 case VE::LDVMrii: in processMI()
478 case VE::STVM512rii: in processMI()
481 case VE::LDVM512rii: in processMI()
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H A DVEFrameLowering.h60 {VE::SX17, 40}, {VE::SX18, 48}, {VE::SX19, 56}, {VE::SX20, 64}, in getCalleeSavedSpillSlots()
61 {VE::SX21, 72}, {VE::SX22, 80}, {VE::SX23, 88}, {VE::SX24, 96}, in getCalleeSavedSpillSlots()
62 {VE::SX25, 104}, {VE::SX26, 112}, {VE::SX27, 120}, {VE::SX28, 128}, in getCalleeSavedSpillSlots()
63 {VE::SX29, 136}, {VE::SX30, 144}, {VE::SX31, 152}, {VE::SX32, 160}, in getCalleeSavedSpillSlots()
64 {VE::SX33, 168}}; in getCalleeSavedSpillSlots()
H A DVERegisterInfo.td10 // Declarations that describe the VE register file
18 let Namespace = "VE";
26 let Namespace = "VE";
34 let Namespace = "VE";
44 let Namespace = "VE";
49 let Namespace = "VE" in {
77 def MISC : RegisterClass<"VE", [i64], 64,
170 def I32 : RegisterClass<"VE", [i32], 32,
178 def F32 : RegisterClass<"VE", [f32], 32,
182 def F128 : RegisterClass<"VE", [f128], 128,
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H A DVEISelLowering.cpp2036 .addReg(VE::SX15) in prepareMBB()
2235 MIB.addReg(VE::SX17); in emitEHSjLjSetJmp()
2278 BuildMI(RestoreMBB, DL, TII->get(VE::LDrii), VE::SX17); in emitEHSjLjSetJmp()
2279 MIB.addReg(VE::SX10); in emitEHSjLjSetJmp()
2310 Register FP = VE::SX9; in emitEHSjLjLongJmp()
2311 Register SP = VE::SX11; in emitEHSjLjLongJmp()
2342 BuildMI(*ThisMBB, MI, DL, TII->get(VE::ORri), VE::SX10) in emitEHSjLjLongJmp()
2460 BuildMI(TrapBB, DL, TII->get(VE::BSICrii), VE::SX10) in emitSjLjDispatchBlock()
2483 BuildMI(DispatchBB, DL, TII->get(VE::GETGOT), VE::SX15); in emitSjLjDispatchBlock()
2528 .addReg(VE::SX15) in emitSjLjDispatchBlock()
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H A DVEAsmPrinter.cpp86 SICInst.setOpcode(VE::SIC); in emitSIC()
94 BSICInst.setOpcode(VE::BSICrii); in emitBSIC()
106 LEAInst.setOpcode(VE::LEAzii); in emitLEAzzi()
118 LEASLInst.setOpcode(VE::LEASLzii); in emitLEASLzzi()
130 LEAInst.setOpcode(VE::LEAzii); in emitLEAzii()
143 LEASLInst.setOpcode(VE::LEASLrri); in emitLEASLrri()
164 emitBinary(OutStreamer, VE::ANDrm, RS1, Imm, RD, STI); in emitANDrm()
293 MCOperand RegLR = MCOperand::createReg(VE::SX10); // LR in lowerGETTLSAddrAndEmitMCInsts()
337 case VE::GETGOT: in emitInstruction()
340 case VE::GETFUNPLT: in emitInstruction()
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H A DVE.td1 //===-- VE.td - Describe the VE Target Machine -------------*- tablegen -*-===//
19 // VE Subtarget features.
36 // Use both VE register name matcher to accept "S0~S63" register names
43 // VE processors supported.
61 def VE : Target {
H A DCMakeLists.txt1 add_llvm_component_group(VE)
3 set(LLVM_TARGET_DEFINITIONS VE.td)
44 VE
H A DVECallingConv.td1 //===-- VECallingConv.td - Calling Conventions VE ----------*- tablegen -*-===//
9 // This describes the calling conventions for the VE architectures.
14 // Aurora VE
24 ///// C Calling Convention (VE ABI v2.1) /////
26 // Reference: https://www.nec.com/en/global/prod/hpc/aurora/document/VE-ABI_v2.1.pdf
58 ///// Standard vararg C Calling Convention (VE ABI v2.1) /////
H A DLVLGen.cpp57 return VE::NoRegister; in getVL()
78 if (Reg != VE::NoRegister) { in runOnMachineBasicBlock()
91 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(VE::LVLr)).addReg(Reg); in runOnMachineBasicBlock()
/llvm-project-15.0.7/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp102 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
103 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
104 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
105 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
106 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
107 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
114 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6,
126 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
127 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
128 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
[all …]
/llvm-project-15.0.7/llvm/lib/Bitcode/Writer/
H A DBitcodeWriter.cpp163 ValueEnumerator VE; member in __anon33774a8c0111::ModuleBitcodeWriterBase
797 VE.getAttributeGroups(); in writeAttributeGroupTable()
2311 if (!VE.hasMDs()) in writeFunctionMetadata()
2731 unsigned ValID = VE.getValueID(V); in pushValueAndType()
2779 VE.setInstructionID(&I); in writeInstruction()
3256 Record[0] = VE.getValueID(&F); in writeGlobalValueSymbolTable()
3336 return !VE.UseListOrders.empty() && VE.UseListOrders.back().F == F; in writeUseListBlock()
3345 VE.UseListOrders.pop_back(); in writeUseListBlock()
3359 VE.incorporateFunction(F); in writeFunction()
3452 VE.purgeFunction(); in writeFunction()
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/llvm-project-15.0.7/llvm/lib/Target/DirectX/DXILWriter/
H A DDXILBitcodeWriter.cpp106 ValueEnumerator VE; member in llvm::dxil::DXILBitcodeWriter
142 VE.EnumerateType(El.second); in DXILBitcodeWriter()
555 return VE.getTypeID(T); in getTypeID()
559 return VE.getTypeID(I8PtrTy); in getTypeID()
566 return VE.getTypeID(T); in getTypeID()
895 VE.getAttributeGroups(); in writeAttributeGroupTable()
1849 if (!VE.hasMDs()) in writeFunctionMetadata()
2250 VE.setInstructionID(&I); in writeInstruction()
2649 return !VE.UseListOrders.empty() && VE.UseListOrders.back().F == F; in writeUseListBlock()
2666 VE.incorporateFunction(F); in writeFunction()
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/VE/
H A Ddisable_lv.ll1 ; RUN: opt < %s -loop-vectorize -mtriple=ve-linux -S | FileCheck %s -check-prefix=VE
4 ; Make sure LV does not trigger for VE on an appealing loop that vectorizes for x86 AVX.
6 ; TODO: Remove this test once VE vector isel is deemed stable.
8 ; VE-NOT: llvm.loop.isvectorized
/llvm-project-15.0.7/llvm/include/llvm/BinaryFormat/ELFRelocs/
H A DVE.def8 // - System V Application Binary Interface - VE Architecture
10 // - ELF Handling For Thread-Local Storage - VE Architecture
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/VE/
H A Ddisable_slp.ll1 ; RUN: opt < %s -basic-aa -slp-vectorizer -mtriple=ve-linux -S | FileCheck %s -check-prefix=VE
4 ; Make sure SLP does not trigger for VE on an appealing set of combinable loads
7 ; TODO: Remove this test once VE vector isel is deemed stable.
9 ; VE-NOT: x double
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DBuiltinsVE.def1 //===--- BuiltinsVE.def - VE Builtin function database ----------*- C++ -*-===//
9 // This file defines the VE-specific builtin function database. Users of
/llvm-project-15.0.7/compiler-rt/cmake/
H A Dcrt-config-ix.cmake30 set(VE ve) variable
33 ${PPC64} ${RISCV32} ${RISCV64} ${VE} ${HEXAGON})

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