Lines Matching refs:VE
85 addRegisterClass(MVT::i32, &VE::I32RegClass); in initRegisterClasses()
86 addRegisterClass(MVT::i64, &VE::I64RegClass); in initRegisterClasses()
87 addRegisterClass(MVT::f32, &VE::F32RegClass); in initRegisterClasses()
88 addRegisterClass(MVT::f64, &VE::I64RegClass); in initRegisterClasses()
89 addRegisterClass(MVT::f128, &VE::F128RegClass); in initRegisterClasses()
93 addRegisterClass(VecVT, &VE::V64RegClass); in initRegisterClasses()
94 addRegisterClass(MVT::v256i1, &VE::VMRegClass); in initRegisterClasses()
95 addRegisterClass(MVT::v512i1, &VE::VM512RegClass); in initRegisterClasses()
404 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerReturn()
482 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerFormalArguments()
549 .Case("sp", VE::SX11) // Stack pointer in getRegisterByName()
550 .Case("fp", VE::SX9) // Frame pointer in getRegisterByName()
551 .Case("sl", VE::SX8) // Stack limit in getRegisterByName()
552 .Case("lr", VE::SX10) // Link register in getRegisterByName()
553 .Case("tp", VE::SX14) // Thread pointer in getRegisterByName()
554 .Case("outer", VE::SX12) // Outer regiser in getRegisterByName()
555 .Case("info", VE::SX17) // Info area register in getRegisterByName()
556 .Case("got", VE::SX15) // Global offset table register in getRegisterByName()
557 .Case("plt", VE::SX16) // Procedure linkage table register in getRegisterByName()
673 RegsToPass.push_back(std::make_pair(VE::SX12, Callee)); in LowerCall()
704 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerCall()
722 SDValue StackPtr = DAG.getRegister(VE::SX11, PtrVT); in LowerCall()
830 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerCall()
903 setStackPointerRegisterToSaveRestore(VE::SX11); in VETargetLowering()
1104 return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other, in lowerATOMIC_FENCE()
1110 return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other, in lowerATOMIC_FENCE()
1119 return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other, in lowerATOMIC_FENCE()
1280 Chain = DAG.getCopyFromReg(Chain, DL, VE::SX0, PtrVT, Chain.getValue(1)); in lowerToTLSGeneralDynamicModel()
1332 SDValue SubRegEven = DAG.getTargetConstant(VE::sub_even, DL, MVT::i32); in lowerLoadF128()
1333 SDValue SubRegOdd = DAG.getTargetConstant(VE::sub_odd, DL, MVT::i32); in lowerLoadF128()
1381 VM = DAG.getMachineNode(VE::LVMir_m, DL, MVT::i64, in lowerLoadI1()
1402 VM = DAG.getMachineNode(VE::LVMyir_y, DL, MVT::i64, in lowerLoadI1()
1445 SDValue SubRegEven = DAG.getTargetConstant(VE::sub_even, DL, MVT::i32); in lowerStoreF128()
1446 SDValue SubRegOdd = DAG.getTargetConstant(VE::sub_odd, DL, MVT::i32); in lowerStoreF128()
1496 DAG.getMachineNode(VE::SVMmi, DL, MVT::i64, StNode->getValue(), in lowerStoreI1()
1511 DAG.getMachineNode(VE::SVMyi, DL, MVT::i64, StNode->getValue(), in lowerStoreI1()
1565 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(VE::SX9, PtrVT), in lowerVASTART()
2018 const TargetRegisterClass *RC = &VE::I64RegClass; in prepareMBB()
2028 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareMBB()
2032 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
2035 BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Result) in prepareMBB()
2036 .addReg(VE::SX15) in prepareMBB()
2044 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareMBB()
2048 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
2051 BuildMI(MBB, I, DL, TII->get(VE::LEASLrii), Result) in prepareMBB()
2068 const TargetRegisterClass *RC = &VE::I64RegClass; in prepareSymbol()
2080 BuildMI(MBB, I, DL, TII->get(VE::GETFUNPLT), Result) in prepareSymbol()
2089 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2093 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
2096 BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Result) in prepareSymbol()
2097 .addReg(VE::SX15) in prepareSymbol()
2109 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2113 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
2116 BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Tmp3) in prepareSymbol()
2117 .addReg(VE::SX15) in prepareSymbol()
2120 BuildMI(MBB, I, DL, TII->get(VE::LDrii), Result) in prepareSymbol()
2132 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2136 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
2139 BuildMI(MBB, I, DL, TII->get(VE::LEASLrii), Result) in prepareSymbol()
2159 MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii)); in setupEntryBlockForSjLj()
2231 MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii)); in emitEHSjLjSetJmp()
2235 MIB.addReg(VE::SX17); in emitEHSjLjSetJmp()
2240 MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii)); in emitEHSjLjSetJmp()
2251 BuildMI(*ThisMBB, MI, DL, TII->get(VE::EH_SjLj_Setup)).addMBB(RestoreMBB); in emitEHSjLjSetJmp()
2259 BuildMI(MainMBB, DL, TII->get(VE::LEAzii), MainDestReg) in emitEHSjLjSetJmp()
2266 BuildMI(*SinkMBB, SinkMBB->begin(), DL, TII->get(VE::PHI), DstReg) in emitEHSjLjSetJmp()
2278 BuildMI(RestoreMBB, DL, TII->get(VE::LDrii), VE::SX17); in emitEHSjLjSetJmp()
2279 MIB.addReg(VE::SX10); in emitEHSjLjSetJmp()
2284 BuildMI(RestoreMBB, DL, TII->get(VE::LEAzii), RestoreDestReg) in emitEHSjLjSetJmp()
2288 BuildMI(RestoreMBB, DL, TII->get(VE::BRCFLa_t)).addMBB(SinkMBB); in emitEHSjLjSetJmp()
2308 Register Tmp = MRI.createVirtualRegister(&VE::I64RegClass); in emitEHSjLjLongJmp()
2310 Register FP = VE::SX9; in emitEHSjLjLongJmp()
2311 Register SP = VE::SX11; in emitEHSjLjLongJmp()
2327 MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), FP); in emitEHSjLjLongJmp()
2334 MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), Tmp); in emitEHSjLjLongJmp()
2342 BuildMI(*ThisMBB, MI, DL, TII->get(VE::ORri), VE::SX10) in emitEHSjLjLongJmp()
2347 MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), SP); in emitEHSjLjLongJmp()
2354 BuildMI(*ThisMBB, MI, DL, TII->get(VE::BCFLari_t)) in emitEHSjLjLongJmp()
2460 BuildMI(TrapBB, DL, TII->get(VE::BSICrii), VE::SX10) in emitSjLjDispatchBlock()
2477 BuildMI(DispatchBB, DL, TII->get(VE::NOP)) in emitSjLjDispatchBlock()
2483 BuildMI(DispatchBB, DL, TII->get(VE::GETGOT), VE::SX15); in emitSjLjDispatchBlock()
2487 const TargetRegisterClass *RC = &VE::I64RegClass; in emitSjLjDispatchBlock()
2489 addFrameReference(BuildMI(DispatchBB, DL, TII->get(VE::LDLZXrii), IReg), FI, in emitSjLjDispatchBlock()
2492 BuildMI(DispatchBB, DL, TII->get(VE::BRCFLir_t)) in emitSjLjDispatchBlock()
2500 BuildMI(DispatchBB, DL, TII->get(VE::LEAzii), TmpReg) in emitSjLjDispatchBlock()
2504 BuildMI(DispatchBB, DL, TII->get(VE::BRCFLrr_t)) in emitSjLjDispatchBlock()
2520 BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1) in emitSjLjDispatchBlock()
2524 BuildMI(DispContBB, DL, TII->get(VE::ANDrm), Tmp2) in emitSjLjDispatchBlock()
2527 BuildMI(DispContBB, DL, TII->get(VE::LEASLrri), BReg) in emitSjLjDispatchBlock()
2528 .addReg(VE::SX15) in emitSjLjDispatchBlock()
2536 BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1) in emitSjLjDispatchBlock()
2540 BuildMI(DispContBB, DL, TII->get(VE::ANDrm), Tmp2) in emitSjLjDispatchBlock()
2543 BuildMI(DispContBB, DL, TII->get(VE::LEASLrii), BReg) in emitSjLjDispatchBlock()
2559 BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1) in emitSjLjDispatchBlock()
2562 BuildMI(DispContBB, DL, TII->get(VE::LDrri), TReg) in emitSjLjDispatchBlock()
2566 BuildMI(DispContBB, DL, TII->get(VE::BCFLari_t)) in emitSjLjDispatchBlock()
2585 BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1) in emitSjLjDispatchBlock()
2588 BuildMI(DispContBB, DL, TII->get(VE::LDLZXrri), OReg) in emitSjLjDispatchBlock()
2595 BuildMI(DispContBB, DL, TII->get(VE::ADDSLrr), TReg) in emitSjLjDispatchBlock()
2598 BuildMI(DispContBB, DL, TII->get(VE::BCFLari_t)) in emitSjLjDispatchBlock()
2672 case VE::EH_SjLj_LongJmp: in EmitInstrWithCustomInserter()
2674 case VE::EH_SjLj_SetJmp: in EmitInstrWithCustomInserter()
2676 case VE::EH_SjLj_Setup_Dispatch: in EmitInstrWithCustomInserter()
2786 SDValue SubI32 = DAG.getTargetConstant(VE::sub_i32, DL, MVT::i32); in combineTRUNCATE()
2831 RC = &VE::I64RegClass; in getRegForInlineAsmConstraint()
2834 RC = &VE::V64RegClass; in getRegForInlineAsmConstraint()
2902 SDValue(DAG.getMachineNode(VE::LVSvr, DL, MVT::i64, {Vec, HalfIdx}), 0); in lowerEXTRACT_VECTOR_ELT()
2910 SDValue SubI32 = DAG.getTargetConstant(VE::sub_i32, DL, MVT::i32); in lowerEXTRACT_VECTOR_ELT()
2960 SDValue(DAG.getMachineNode(VE::LVSvr, DL, MVT::i64, {Vec, HalfIdx}), 0); in lowerINSERT_VECTOR_ELT()
2971 SDValue(DAG.getMachineNode(VE::LSVrr_v, DL, Vec.getSimpleValueType(), in lowerINSERT_VECTOR_ELT()