36 VERegisterInfo::VERegisterInfo() : VEGenRegisterInfo(VE::SX10) {}  in VERegisterInfo()
70       VE::SX8,  // Stack limit  in getReservedRegs()
71       VE::SX9,  // Frame pointer  in getReservedRegs()
72       VE::SX10, // Link register (return address)  in getReservedRegs()
73       VE::SX11, // Stack pointer  in getReservedRegs()
76       VE::SX12, // Outer register  in getReservedRegs()
77       VE::SX13, // Id register for dynamic linker  in getReservedRegs()
79       VE::SX14, // Thread pointer  in getReservedRegs()
80       VE::SX15, // Global offset table register  in getReservedRegs()
81       VE::SX16, // Procedure linkage table register  in getReservedRegs()
82       VE::SX17, // Linkage-area register  in getReservedRegs()
93   Reserved.set(VE::VM0);  in getReservedRegs()
94   Reserved.set(VE::VMP0);  in getReservedRegs()
101   case VE::VM0:  in isConstantPhysReg()
102   case VE::VMP0:  in isConstantPhysReg()
112   return &VE::I64RegClass;  in getPointerRegClass()
122     using namespace llvm::VE;  in offsetToDisp()
198       : TII(TII), TRI(TRI), DL(DL), MBB(MBB), II(II), clobber(VE::SX13) {}  in EliminateFrameIndex()
220   build(VE::LEAzii, clobber).addImm(0).addImm(0).addImm(Lo_32(Offset));  in prepareReplaceFI()
221   build(VE::ANDrm, clobber).addReg(clobber).addImm(M0(32));  in prepareReplaceFI()
222   build(VE::LEASLrri, clobber)  in prepareReplaceFI()
245   assert(MI.getOpcode() == VE::STQrii);  in processSTQ()
251   Register SrcHiReg = getSubReg(SrcReg, VE::sub_even);  in processSTQ()
252   Register SrcLoReg = getSubReg(SrcReg, VE::sub_odd);  in processSTQ()
255       build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(SrcLoReg);  in processSTQ()
258   MI.setDesc(get(VE::STrii));  in processSTQ()
266   assert(MI.getOpcode() == VE::LDQrii);  in processLDQ()
272   Register DestHiReg = getSubReg(DestReg, VE::sub_even);  in processLDQ()
273   Register DestLoReg = getSubReg(DestReg, VE::sub_odd);  in processLDQ()
276       build(VE::LDrii, DestLoReg).addReg(FrameReg).addImm(0).addImm(0);  in processLDQ()
278   MI.setDesc(get(VE::LDrii));  in processLDQ()
286   assert(MI.getOpcode() == VE::STVMrii);  in processSTVM()
307   Register TmpReg = VE::SX16;  in processSTVM()
309     build(VE::SVMmr, TmpReg).addReg(SrcReg).addImm(i);  in processSTVM()
311         build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(  in processSTVM()
316   build(VE::SVMmr, TmpReg).addReg(SrcReg, getKillRegState(isKill)).addImm(3);  in processSTVM()
317   MI.setDesc(get(VE::STrii));  in processSTVM()
324   assert(MI.getOpcode() == VE::LDVMrii);  in processLDVM()
344   unsigned TmpReg = VE::SX16;  in processLDVM()
348           build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0);  in processLDVM()
353       MI.setDesc(get(VE::LDrii));  in processLDVM()
359       build(VE::LVMir, DestReg).addImm(i).addReg(TmpReg, getKillRegState(true));  in processLDVM()
361       build(VE::LVMir_m, DestReg)  in processLDVM()
366       BuildMI(*MI.getParent(), std::next(II), DL, get(VE::LVMir_m), DestReg)  in processLDVM()
376   assert(MI.getOpcode() == VE::STVM512rii);  in processSTVM512()
382   Register SrcLoReg = getSubReg(SrcReg, VE::sub_vm_odd);  in processSTVM512()
383   Register SrcHiReg = getSubReg(SrcReg, VE::sub_vm_even);  in processSTVM512()
387   Register TmpReg = VE::SX16;  in processSTVM512()
391     LastMI = build(VE::SVMmr, TmpReg).addReg(SrcLoReg).addImm(i);  in processSTVM512()
393         build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(  in processSTVM512()
402     build(VE::SVMmr, TmpReg).addReg(SrcHiReg).addImm(i);  in processSTVM512()
404         build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(  in processSTVM512()
409   LastMI = build(VE::SVMmr, TmpReg).addReg(SrcHiReg).addImm(3);  in processSTVM512()
415   MI.setDesc(get(VE::STrii));  in processSTVM512()
422   assert(MI.getOpcode() == VE::LDVM512rii);  in processLDVM512()
428   Register DestLoReg = getSubReg(DestReg, VE::sub_vm_odd);  in processLDVM512()
429   Register DestHiReg = getSubReg(DestReg, VE::sub_vm_even);  in processLDVM512()
432   Register TmpReg = VE::SX16;  in processLDVM512()
433   build(VE::IMPLICIT_DEF, DestReg);  in processLDVM512()
436         build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0);  in processLDVM512()
438     build(VE::LVMir_m, DestLoReg)  in processLDVM512()
446         build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0);  in processLDVM512()
448     build(VE::LVMir_m, DestHiReg)  in processLDVM512()
454   MI.setDesc(get(VE::LDrii));  in processLDVM512()
456   BuildMI(*MI.getParent(), std::next(II), DL, get(VE::LVMir_m), DestHiReg)  in processLDVM512()
466   case VE::STQrii:  in processMI()
469   case VE::LDQrii:  in processMI()
472   case VE::STVMrii:  in processMI()
475   case VE::LDVMrii:  in processMI()
478   case VE::STVM512rii:  in processMI()
481   case VE::LDVM512rii:  in processMI()
515   return VE::SX9;  in getFrameRegister()