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Searched refs:UseOp (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCPreEmitPeephole.cpp296 const MachineOperand *UseOp = in addLinkerOpt() local
300 if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg && in addLinkerOpt()
301 UseOp->isUse() && UseOp->isKill()) { in addLinkerOpt()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineTraceMetrics.cpp630 unsigned UseOp; member
632 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) in DataDep()
633 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep()
636 DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp) in DataDep()
637 : UseOp(UseOp) { in DataDep()
804 .computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI, Dep.UseOp); in updateDepth()
960 Dep.UseOp); in pushDepHeight()
1191 &PHI, Dep.UseOp); in getPHIDepth()
H A DScheduleDAGInstrs.cpp250 int UseOp = I->OpIdx; in addPhysRegDataDeps() local
253 if (UseOp < 0) in addPhysRegDataDeps()
265 (UseMIDesc && UseOp >= ((int)UseMIDesc->getNumOperands()) && in addPhysRegDataDeps()
269 RegUse, UseOp)); in addPhysRegDataDeps()
273 ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep); in addPhysRegDataDeps()
H A DTwoAddressInstructionPass.cpp382 MachineOperand *UseOp = nullptr; in findOnlyInterestingUse() local
388 UseOp = &MO; in findOnlyInterestingUse()
390 if (!UseOp) in findOnlyInterestingUse()
392 MachineInstr &UseMI = *UseOp->getParent(); in findOnlyInterestingUse()
407 unsigned Src2 = UseMI.getOperandNo(UseOp); in findOnlyInterestingUse()
H A DModuloSchedule.cpp84 for (MachineOperand &UseOp : MRI.use_operands(Reg)) { in expand()
85 MachineInstr *UseMI = UseOp.getParent(); in expand()
1129 for (MachineOperand &UseOp : in rewriteScheduledInstr()
1131 MachineInstr *UseMI = UseOp.getParent(); in rewriteScheduledInstr()
1169 UseOp.setReg(ReplaceReg); in rewriteScheduledInstr()
1175 UseOp.setReg(SplitReg); in rewriteScheduledInstr()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp554 MachineOperand &UseOp = UseMI->getOperand(UseOpIdx); in tryToFoldACImm() local
555 if (!UseOp.getSubReg() && Def && TII->isFoldableCopy(*Def)) { in tryToFoldACImm()
597 const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx); in foldOperand() local
599 if (!isUseSafeToFold(TII, *UseMI, UseOp)) in foldOperand()
603 if (UseOp.isReg() && OpToFold.isReg()) { in foldOperand()
604 if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister) in foldOperand()
885 UseOp.isImplicit() || in foldOperand()
921 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) { in foldOperand()
922 Register UseReg = UseOp.getReg(); in foldOperand()
929 if (UseOp.getSubReg() == AMDGPU::sub0) { in foldOperand()
[all …]
H A DAMDGPUResourceUsageAnalysis.cpp75 for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) { in hasAnyNonFlatUseOfReg() local
76 if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent())) in hasAnyNonFlatUseOfReg()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp5331 int UseOp = -1; in getPartialRegUpdateClearance() local
5343 UseOp = MI.findRegisterUseOperandIdx(Reg, false, TRI); in getPartialRegUpdateClearance()
5348 UseOp = 3; in getPartialRegUpdateClearance()
5356 if (UseOp != -1 && MI.getOperand(UseOp).readsReg()) in getPartialRegUpdateClearance()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp11426 SDValue UseOp = User->getOperand(i); in ExtendUsesToFormExtLoad() local
11427 if (UseOp == N0) in ExtendUsesToFormExtLoad()
11429 if (!isa<ConstantSDNode>(UseOp)) in ExtendUsesToFormExtLoad()