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Searched refs:TmpVGPR (Results 1 – 2 of 2) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp90 Register TmpVGPR = AMDGPU::NoRegister; member
177 if (TmpVGPR) { in prepare()
183 TmpVGPR = AMDGPU::VGPR0; in prepare()
195 RS->setRegUsed(TmpVGPR); in prepare()
213 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
230 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
257 I.addReg(TmpVGPR, RegState::ImplicitKill); in restore()
265 I.addReg(TmpVGPR, RegState::ImplicitKill); in restore()
1748 SB.TmpVGPR) in spillSGPR()
1890 SB.TmpVGPR) in spillEmergencySGPR()
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H A DSIFrameLowering.cpp815 MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister( in emitPrologue() local
817 if (!TmpVGPR) in emitPrologue()
820 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR) in emitPrologue()
823 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, DL, TmpVGPR, in emitPrologue()
1008 MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister( in emitEpilogue() local
1010 if (!TmpVGPR) in emitEpilogue()
1012 buildEpilogRestore(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, DL, TmpVGPR, in emitEpilogue()
1015 .addReg(TmpVGPR, RegState::Kill); in emitEpilogue()