90   Register TmpVGPR = AMDGPU::NoRegister;  member
173     TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0, false);  in prepare()
177     if (TmpVGPR) {  in prepare()
183       TmpVGPR = AMDGPU::VGPR0;  in prepare()
190       RS->assignRegToScavengingIndex(TmpVGPRIndex, TmpVGPR);  in prepare()
195     RS->setRegUsed(TmpVGPR);  in prepare()
213         I.addReg(TmpVGPR, RegState::ImplicitDefine);  in prepare()
230         I.addReg(TmpVGPR, RegState::ImplicitDefine);  in prepare()
257         I.addReg(TmpVGPR, RegState::ImplicitKill);  in restore()
265         I.addReg(TmpVGPR, RegState::ImplicitKill);  in restore()
276       RS->assignRegToScavengingIndex(TmpVGPRIndex, TmpVGPR, &*RestorePt);  in restore()
1328   auto MaterializeVOffset = [&](Register SGPRBase, Register TmpVGPR,  in buildSpillLoadStore()
1337         BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_ADD_U32_e64), TmpVGPR)  in buildSpillLoadStore()
1342         BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR)  in buildSpillLoadStore()
1344         BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_ADD_U32_e32), TmpVGPR)  in buildSpillLoadStore()
1350       BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR)  in buildSpillLoadStore()
1657     buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, false,  in buildVGPRSpillLoadStore()
1662     buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, IsKill,  in buildVGPRSpillLoadStore()
1748                     SB.TmpVGPR)  in spillSGPR()
1751                 .addReg(SB.TmpVGPR, TmpVGPRFlags);  in spillSGPR()
1844                        .addReg(SB.TmpVGPR, getKillRegState(LastSubReg))  in restoreSGPR()
1890                   SB.TmpVGPR)  in spillEmergencySGPR()
1893               .addReg(SB.TmpVGPR, TmpVGPRFlags);  in spillEmergencySGPR()
1925                      .addReg(SB.TmpVGPR, getKillRegState(LastSubReg))  in spillEmergencySGPR()