| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 426 DestReg = TempReg; in materializeGV()
1611 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]); in fastLowerIntrinsicCall()
1633 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00); in fastLowerIntrinsicCall()
1634 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]); in fastLowerIntrinsicCall()
1637 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8); in fastLowerIntrinsicCall()
1640 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]); in fastLowerIntrinsicCall()
1641 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]); in fastLowerIntrinsicCall()
1972 if (!TempReg) in selectShift()
1980 Op0Reg = TempReg; in selectShift()
2100 VReg = TempReg; in getRegEnsuringSimpleIntegerWidening()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 690 SingleScratchReg = ScratchReg == TempReg; in emitPrologue()
808 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
870 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
902 .addDef(TempReg) in emitPrologue()
937 .addReg(TempReg, RegState::Kill); in emitPrologue()
1278 Register &TempReg) { in inlineStackProbe() argument
1287 .addReg(TempReg) in inlineStackProbe()
1348 Register &FinalStackPtr = TempReg; in inlineStackProbe()
1595 SingleScratchReg = ScratchReg == TempReg; in emitEpilogue()
1766 BuildMI(MBB, MBBI, dl, LoadWordInst, TempReg) in emitEpilogue()
[all …]
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| H A D | PPCISelDAGToDAG.cpp | 467 Register TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); in getGlobalBaseReg() local
470 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg); in getGlobalBaseReg()
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| H A D | PPCISelLowering.cpp | 12115 Register TempReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca() local
12116 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS), TempReg) in emitProbedAlloca()
12120 .addReg(TempReg) in emitProbedAlloca()
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| /llvm-project-15.0.7/bolt/lib/Target/X86/ |
| H A D | X86MCPlusBuilder.cpp | 3264 MCPhysReg TempReg = getIntArgRegister(0); in createInstrumentedIndirectCall() local
3275 createPushRegister(Insts.back(), TempReg, 8); in createInstrumentedIndirectCall()
3284 convertIndirectCallToLoad(Insts.back(), TempReg); in createInstrumentedIndirectCall()
3290 createPushRegister(Insts.back(), TempReg, 8); in createInstrumentedIndirectCall()
3294 createPushRegister(Insts.back(), TempReg, 8); in createInstrumentedIndirectCall()
3308 const MCPhysReg TempReg = getIntArgRegister(0); in createInstrumentedIndCallHandlerExitBB() local
3318 createPopRegister(Insts[1], TempReg, 8); in createInstrumentedIndCallHandlerExitBB()
3320 createSwap(Insts[3], TempReg, X86::RSP, 0); in createInstrumentedIndCallHandlerExitBB()
3327 const MCPhysReg TempReg = getIntArgRegister(0); in createInstrumentedIndTailCallHandlerExitBB() local
3336 createPopRegister(Insts[2], TempReg, 8); in createInstrumentedIndTailCallHandlerExitBB()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetMachine.cpp | 1480 Register TempReg; in parseMachineFunctionInfo() local
1481 if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) { in parseMachineFunctionInfo()
1485 RegVal = TempReg; in parseMachineFunctionInfo()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1727 Register TempReg = MI.getOperand(1).getReg(); in ExpandCMP_SWAP() local
1791 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg) in ExpandCMP_SWAP()
1801 .addReg(TempReg, RegState::Kill) in ExpandCMP_SWAP()
1857 Register TempReg = MI.getOperand(1).getReg(); in ExpandCMP_SWAP_64() local
1915 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg); in ExpandCMP_SWAP_64()
1922 .addReg(TempReg, RegState::Kill) in ExpandCMP_SWAP_64()
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| H A D | ARMFastISel.cpp | 2970 Register TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass); in ARMLowerPICELF() local
2973 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), TempReg) in ARMLowerPICELF()
2986 .addReg(TempReg) in ARMLowerPICELF()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 2584 unsigned TempReg = Inst.getOperand(1).getReg(); in validateInstruction() local
2585 if (DestReg == TempReg) { in validateInstruction()
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | GlobalISelEmitter.cpp | 3631 unsigned TempReg);
|