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Searched refs:TRUNCATE (Results 1 – 25 of 55) sorted by relevance

123

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1717 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, in getCastInstrCost()
1718 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, in getCastInstrCost()
1719 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, in getCastInstrCost()
1720 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, in getCastInstrCost()
1721 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, in getCastInstrCost()
1722 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, in getCastInstrCost()
1723 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, in getCastInstrCost()
1724 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, in getCastInstrCost()
1725 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, in getCastInstrCost()
1829 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, in getCastInstrCost()
[all …]
H A DX86ISelLowering.cpp2353 ISD::TRUNCATE, in X86TargetLowering()
4960 if (Op == ISD::TRUNCATE) { in MatchingStackOffset()
9162 case ISD::TRUNCATE: in findEltLoadSrc()
23534 case ISD::TRUNCATE: { in MatchVectorAllZeroTest()
25312 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) { in LowerSELECT()
29034 ISD::TRUNCATE, dl, VT, in LowerMUL()
31611 ISD::TRUNCATE, DL, MVT::i8, in LowerPARITY()
32553 case ISD::TRUNCATE: { in ReplaceNodeResults()
42186 case ISD::TRUNCATE: in checkBitcastSrcVectorSize()
42251 case ISD::TRUNCATE: in signExtendBitcastSrcVector()
[all …]
H A DX86ISelDAGToDAG.cpp2382 RHS.getNode()->getOpcode() == ISD::TRUNCATE || in matchAddressRecursively()
2852 if (N.getOpcode() == ISD::TRUNCATE) { in selectRelocImm()
2921 if (N->getOpcode() == ISD::TRUNCATE) in isSExtAbsoluteSymbolRef()
3515 if (V->getOpcode() == ISD::TRUNCATE && checkOneUse(V)) { in matchBitExtract()
3579 if (NBits.getOpcode() == ISD::TRUNCATE) in matchBitExtract()
3675 NBits = CurDAG->getNode(ISD::TRUNCATE, DL, MVT::i8, NBits); in matchBitExtract()
3773 Extract = CurDAG->getNode(ISD::TRUNCATE, DL, NVT, Extract); in matchBitExtract()
3982 if (ShiftAmt->getOpcode() == ISD::TRUNCATE) in tryShiftAmountMod()
4010 if (Add1.getOpcode() == ISD::TRUNCATE) { in tryShiftAmountMod()
4041 NewShiftAmt = CurDAG->getNode(ISD::TRUNCATE, DL, MVT::i8, NewShiftAmt); in tryShiftAmountMod()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp571 {ISD::TRUNCATE, MVT::v4i32, MVT::v4i16, 0}, in getCastInstrCost()
572 {ISD::TRUNCATE, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
573 {ISD::TRUNCATE, MVT::v8i16, MVT::v8i8, 0}, in getCastInstrCost()
574 {ISD::TRUNCATE, MVT::v8i32, MVT::v8i16, 1}, in getCastInstrCost()
575 {ISD::TRUNCATE, MVT::v8i32, MVT::v8i8, 1}, in getCastInstrCost()
576 {ISD::TRUNCATE, MVT::v16i32, MVT::v16i8, 3}, in getCastInstrCost()
675 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
855 { ISD::TRUNCATE, MVT::i32, MVT::i64, 0 }, in getCastInstrCost()
856 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 }, in getCastInstrCost()
857 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 }, in getCastInstrCost()
[all …]
H A DARMSelectionDAGInfo.cpp106 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src); in EmitSpecializedLibcall()
312 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src)); in EmitTargetCodeForMemset()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp1605 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
1606 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
1607 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
1608 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
1611 { ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i16, 1 }, in getCastInstrCost()
1612 { ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i32, 1 }, in getCastInstrCost()
1613 { ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i64, 1 }, in getCastInstrCost()
1614 { ISD::TRUNCATE, MVT::nxv4i1, MVT::nxv4i16, 1 }, in getCastInstrCost()
1615 { ISD::TRUNCATE, MVT::nxv4i1, MVT::nxv4i32, 1 }, in getCastInstrCost()
1616 { ISD::TRUNCATE, MVT::nxv4i1, MVT::nxv4i64, 2 }, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp1226 setOperationAction(ISD::TRUNCATE, VT, Custom); in AArch64TargetLowering()
1691 setOperationAction(ISD::TRUNCATE, VT, Custom); in addTypeForFixedLengthSVE()
3772 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv); in LowerVectorFP_TO_INT()
5575 case ISD::TRUNCATE: in LowerOperation()
14279 (N0->getOpcode() == ISD::TRUNCATE && in performMulCombine()
15199 N1Opc == ISD::TRUNCATE) { in performConcatVectorsCombine()
15211 return DAG.getNode(ISD::TRUNCATE, dl, VT, in performConcatVectorsCombine()
18263 (CTTZ.getOpcode() == ISD::TRUNCATE && in foldCSELofCTTZ()
18273 SDValue X = CTTZ.getOpcode() == ISD::TRUNCATE in foldCSELofCTTZ()
18538 if (Op->getOpcode() == ISD::TRUNCATE && in getTestBitOperand()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp260 if (Op == ISD::TRUNCATE) { in MatchingStackOffset()
858 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); in LowerCallResult()
1449 if (Op0.getOpcode() == ISD::TRUNCATE) in LowerAndToBTST()
1451 if (Op1.getOpcode() == ISD::TRUNCATE) in LowerAndToBTST()
1624 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { in hasNonFlagsUse()
1694 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) { in EmitTest()
1930 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, NewSetCC); in LowerSETCC()
1953 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in LowerSETCC()
2020 if (V.getOpcode() != ISD::TRUNCATE) in isTruncWithZeroHighBitsInput()
2211 Op2.getOpcode() == ISD::TRUNCATE) { in LowerSELECT()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp3387 if (Op1.getOpcode() == ISD::TRUNCATE && in foldSubToUSubSat()
5289 if (HandOpcode == ISD::TRUNCATE) { in hoistLogicOpWithSameOpcodeHands()
7520 if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE && in MatchRotate()
7898 case ISD::TRUNCATE: in stripTruncAndExt()
8826 if (N1.getOpcode() == ISD::TRUNCATE && in visitRotate()
8908 if (N1.getOpcode() == ISD::TRUNCATE && in visitSHL()
9387 if (N1.getOpcode() == ISD::TRUNCATE && in visitSRA()
9397 if (N0.getOpcode() == ISD::TRUNCATE && in visitSRA()
12521 if (N0.getOpcode() == ISD::TRUNCATE) in visitANY_EXTEND()
13180 if (N0.getOpcode() == ISD::TRUNCATE) in visitTRUNCATE()
[all …]
H A DTargetLowering.cpp2353 case ISD::TRUNCATE: { in SimplifyDemandedBits()
3402 case ISD::TRUNCATE: in SimplifyDemandedVectorElts()
4485 if (Op0.getOpcode() == ISD::TRUNCATE) in SimplifySetCC()
4762 return DAG.getNode(ISD::TRUNCATE, dl, VT, in SimplifySetCC()
4772 return DAG.getNode(ISD::TRUNCATE, dl, VT, in SimplifySetCC()
5876 return DAG.getNode(ISD::TRUNCATE, dl, VT, Y); in BuildSDIV()
6034 return DAG.getNode(ISD::TRUNCATE, dl, VT, Y); in BuildUDIV()
6981 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LHS); in expandMUL_LOHI()
7024 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH); in expandMUL_LOHI()
7026 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH); in expandMUL_LOHI()
[all …]
H A DLegalizeDAG.cpp644 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value); in LegalizeStoreOps()
650 Value = DAG.getNode(ISD::TRUNCATE, dl, in LegalizeStoreOps()
1643 SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit); in ExpandFCOPYSIGN()
4500 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); in PromoteNode()
4512 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); in PromoteNode()
4541 TruncOp = ISD::TRUNCATE; in PromoteNode()
4590 TruncOp = ISD::TRUNCATE; in PromoteNode()
4614 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); in PromoteNode()
4615 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp2)); in PromoteNode()
4626 TruncOp = ISD::TRUNCATE; in PromoteNode()
[all …]
H A DLegalizeTypes.cpp1028 Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Op); in SplitInteger()
1037 Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi); in SplitInteger()
H A DLegalizeIntegerTypes.cpp103 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; in PromoteIntegerResult()
1369 if (N->getOpcode() == ISD::TRUNCATE) { in PromoteIntRes_TRUNCATE()
1370 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1); in PromoteIntRes_TRUNCATE()
1371 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2); in PromoteIntRes_TRUNCATE()
1410 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res); in PromoteIntRes_TRUNCATE()
1665 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; in PromoteIntegerOperand()
2302 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, Reduce); in PromoteIntOp_VECREDUCE()
2334 return DAG.getNode(ISD::TRUNCATE, DL, VT, Reduce); in PromoteIntOp_VP_REDUCE()
2441 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; in ExpandIntegerResult()
4352 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); in ExpandIntRes_TRUNCATE()
[all …]
H A DLegalizeVectorTypes.cpp108 case ISD::TRUNCATE: in ScalarizeVectorResult()
362 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op); in ScalarizeVecRes_INSERT_VECTOR_ELT()
643 case ISD::TRUNCATE: in ScalarizeVectorOperand()
1045 case ISD::TRUNCATE: in SplitVectorResult()
1756 Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Lo); in SplitVecRes_INSERT_VECTOR_ELT()
1758 Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi); in SplitVecRes_INSERT_VECTOR_ELT()
2697 case ISD::TRUNCATE: in SplitVectorOperand()
3820 case ISD::TRUNCATE: in WidenVectorResult()
4281 Opcode = ISD::TRUNCATE; in WidenVecRes_Convert()
5051 if (N.getOpcode() == ISD::TRUNCATE) in isSETCCorConvertedSETCC()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dbitfieldinsert.ll63 ; test cases which include ISD::TRUNCATE
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp153 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op.getOperand(0)); in lowerUINT_TO_FP()
350 return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes); in customLegalizeToWOp()
386 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Dst)); in ReplaceNodeResults()
396 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Tmp1)); in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h769 TRUNCATE, enumerator
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp461 if (Opcode == ISD::TRUNCATE) { in expandAddress()
645 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base); in getAddressOperands()
779 case ISD::TRUNCATE: { in expandRxSBG()
969 RISBG.Input.getOpcode() != ISD::TRUNCATE) in tryRISBGZero()
1075 RxSBG[I].Input.getOpcode() != ISD::TRUNCATE) in tryRxSBG()
H A DSystemZISelLowering.cpp2489 if (C.Op0.getOpcode() == ISD::TRUNCATE && in adjustICmpTruncate()
2866 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi); in lowerMUL_LOHI32()
2867 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul); in lowerMUL_LOHI32()
3551 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift); in lowerBITCAST()
3871 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1); in lowerSDIVREM()
3988 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerXALUO()
4054 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerADDSUBCARRY()
4113 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op); in lowerCTPOP()
4214 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift); in lowerATOMIC_LOAD_OP()
5239 if (Op.getOpcode() == ISD::TRUNCATE) in tryBuildVectorShuffle()
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp581 setOperationAction(ISD::TRUNCATE, VT, Custom); in RISCVTargetLowering()
776 setOperationAction(ISD::TRUNCATE, VT, Custom); in RISCVTargetLowering()
3238 case ISD::TRUNCATE: in LowerOperation()
3369 return DAG.getNode(ISD::TRUNCATE, DL, VT, FP2Int); in LowerOperation()
4482 return DAG.getNode(ISD::TRUNCATE, DL, VecVT, Vec); in lowerINSERT_VECTOR_ELT()
4646 return DAG.getNode(ISD::TRUNCATE, DL, EltVT, Elt0); in lowerEXTRACT_VECTOR_ELT()
5722 return DAG.getNode(ISD::TRUNCATE, DL, VecVT, Op2); in lowerVECTOR_REVERSE()
6925 S = DAG.getNode(ISD::TRUNCATE, DL, XLenVT, S); in ReplaceNodeResults()
6926 U = DAG.getNode(ISD::TRUNCATE, DL, XLenVT, U); in ReplaceNodeResults()
8540 return DAG.getNode(ISD::TRUNCATE, DL, VT, FpToInt); in performFP_TO_INTCombine()
[all …]
H A DRISCVTargetTransformInfo.cpp288 case ISD::TRUNCATE: in getCastInstrCost()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8783 CWD = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, in LowerFLT_ROUNDS_()
11307 case ISD::TRUNCATE: { in ReplaceNodeResults()
13425 if (N->getOpcode() == ISD::TRUNCATE && in DAGCombineTruncBoolExt()
13511 if (N->getOpcode() == ISD::TRUNCATE) in DAGCombineTruncBoolExt()
13627 if (PromOp.getOpcode() == ISD::TRUNCATE || in DAGCombineTruncBoolExt()
13678 if (N->getOpcode() == ISD::TRUNCATE) in DAGCombineTruncBoolExt()
15138 case ISD::TRUNCATE: in PerformDAGCombine()
15285 if (Trunc->getOpcode() != ISD::TRUNCATE) in PerformDAGCombine()
15288 if (Trunc->getOpcode() != ISD::TRUNCATE || in PerformDAGCombine()
15299 if (Trunc2->getOpcode() != ISD::TRUNCATE || in PerformDAGCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp470 ISD::TRUNCATE, ISD::MUL, in AMDGPUTargetLowering()
2410 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Sign), in LowerINT_TO_FP32()
2701 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FpToInt32); in LowerFP_TO_INT()
2970 if (N0.getOpcode() == ISD::TRUNCATE) { in performAssertSZExtCombine()
3094 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS); in performShlCombine()
3205 return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0); in performTruncateCombine()
3226 return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt); in performTruncateCombine()
3252 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT, in performTruncateCombine()
3263 return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift); in performTruncateCombine()
3476 FFBX = DAG.getNode(ISD::TRUNCATE, DL, VT, FFBX); in getFFBX_U32()
[all …]
H A DSIISelLowering.cpp209 setOperationAction(ISD::TRUNCATE, in SITargetLowering()
2543 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); in LowerFormalArguments()
2548 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); in LowerFormalArguments()
2551 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); in LowerFormalArguments()
5633 return DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src); in lowerADDRSPACECAST()
8524 return DAG.getNode(ISD::TRUNCATE, SL, VT, Op); in getLoadExtOrTrunc()
8631 DAG.getNode(ISD::TRUNCATE, DL, MemVT, NewLD), in LowerLOAD()
10118 case ISD::TRUNCATE: { in isCanonicalized()
10376 return DAG.getNode(ISD::TRUNCATE, SL, VT, Med3); in performIntMed3ImmCombine()
10846 return DAG.getNode(ISD::TRUNCATE, SL, VT, Mad); in getMad64_32()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1913 Ret = DAG.getNode(ISD::TRUNCATE, dl, ProxyRegTruncates[i].value(), Ret); in LowerCall()
2259 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select); in LowerSelect()
2298 SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD); in LowerLOADi1()
2606 Elt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Elt); in LowerFormalArguments()
2614 Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt); in LowerFormalArguments()
4833 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, LHS); in TryMULWIDECombine()
4835 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, RHS); in TryMULWIDECombine()
5038 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); in ReplaceLoadVector()
5151 DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); in ReplaceINTRINSIC_W_CHAIN()
5181 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, in ReplaceINTRINSIC_W_CHAIN()

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