| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 562 unsigned SuperReg = 0; in FindSuitableFreeRegisters() local
564 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) in FindSuitableFreeRegisters()
565 SuperReg = Reg; in FindSuitableFreeRegisters()
586 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
587 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
602 dbgs() << "*** Performing rename " << printReg(SuperReg, TRI) in FindSuitableFreeRegisters()
616 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
638 if (NewSuperReg == SuperReg) continue; in FindSuitableFreeRegisters()
648 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
651 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
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| H A D | PrologEpilogInserter.cpp | 410 for (const MCPhysReg &SuperReg : RegInfo->superregs(Reg)) { in assignCalleeSavedSpillSlots() local
413 if (SavedRegs.test(SuperReg) && CSMask.test(SuperReg)) { in assignCalleeSavedSpillSlots()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 80 Register SuperReg; member
140 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI && in SGPRSpillBuilder()
201 RS->setRegUsed(SuperReg); in prepare()
1692 ? SB.SuperReg in spillSGPR()
1743 ? SB.SuperReg in spillSGPR()
1783 LIS->removeAllRegUnitsForPhysReg(SB.SuperReg); in spillSGPR()
1804 ? SB.SuperReg in restoreSGPR()
1838 ? SB.SuperReg in restoreSGPR()
1863 LIS->removeAllRegUnitsForPhysReg(SB.SuperReg); in restoreSGPR()
1885 ? SB.SuperReg in spillEmergencySGPR()
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| H A D | SIInstrInfo.h | 70 MachineOperand &SuperReg,
76 MachineOperand &SuperReg,
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| H A D | SIInstrInfo.cpp | 4879 MachineOperand &SuperReg, in buildExtractSubReg() argument
4888 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) { in buildExtractSubReg()
4890 .addReg(SuperReg.getReg(), 0, SubIdx); in buildExtractSubReg()
4901 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg()); in buildExtractSubReg()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 328 SDValue SuperReg = SDValue(Load, 0); in selectVLSEG() local
332 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEG()
372 SDValue SuperReg = SDValue(Load, 0); in selectVLSEGFF() local
376 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEGFF()
427 SDValue SuperReg = SDValue(Load, 0); in selectVLXSEG() local
431 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLXSEG()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1494 SDValue SuperReg = SDValue(Ld, 0); in SelectLoad() local
1497 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1530 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoad() local
1532 ReplaceUses(SDValue(N, 0), SuperReg); in SelectPostLoad()
1536 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1589 SDValue SuperReg = SDValue(Load, 0); in SelectPredicatedLoad() local
1592 AArch64::zsub0 + i, DL, VT, SuperReg)); in SelectPredicatedLoad()
1741 SDValue SuperReg = SDValue(Ld, 0); in SelectLoadLane() local
1790 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoadLane() local
1793 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg); in SelectPostLoadLane()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2230 SDValue SuperReg = SDValue(VLd, 0); in SelectVLD() local
2237 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2480 SDValue SuperReg; in SelectVLDSTLane() local
2485 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
2487 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0); in SelectVLDSTLane()
2494 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2496 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2498 Ops.push_back(SuperReg); in SelectVLDSTLane()
2514 SuperReg = SDValue(VLdLn, 0); in SelectVLDSTLane()
2521 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1697 MCRegister SuperReg = in copyPhysReg() local
1700 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
1703 DestReg = SuperReg; in copyPhysReg()
1706 MCRegister SuperReg = in copyPhysReg() local
1709 if (VSXSelfCopyCrash && DestReg == SuperReg) in copyPhysReg()
1712 SrcReg = SuperReg; in copyPhysReg()
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