80   Register SuperReg;  member
121       : SuperReg(Reg), MI(MI), IsKill(IsKill), DL(MI->getDebugLoc()),  in SGPRSpillBuilder()
125     const TargetRegisterClass *RC = TRI.getPhysRegClass(SuperReg);  in SGPRSpillBuilder()
139     assert(SuperReg != AMDGPU::M0 && "m0 should never spill");  in SGPRSpillBuilder()
140     assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI &&  in SGPRSpillBuilder()
141            SuperReg != AMDGPU::EXEC && "exec should never spill");  in SGPRSpillBuilder()
201     RS->setRegUsed(SuperReg);  in prepare()
1681   assert(SpillToVGPR || (SB.SuperReg != SB.MFI.getStackPtrOffsetReg() &&  in spillSGPR()
1682                          SB.SuperReg != SB.MFI.getFrameOffsetReg()));  in spillSGPR()
1692               ? SB.SuperReg  in spillSGPR()
1693               : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in spillSGPR()
1715         MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);  in spillSGPR()
1719         MIB.addReg(SB.SuperReg, getKillRegState(UseKill) | RegState::Implicit);  in spillSGPR()
1743                 ? SB.SuperReg  in spillSGPR()
1744                 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in spillSGPR()
1768           WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState);  in spillSGPR()
1783     LIS->removeAllRegUnitsForPhysReg(SB.SuperReg);  in spillSGPR()
1804               ? SB.SuperReg  in restoreSGPR()
1805               : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in restoreSGPR()
1813         MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);  in restoreSGPR()
1838                 ? SB.SuperReg  in restoreSGPR()
1839                 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in restoreSGPR()
1847           MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);  in restoreSGPR()
1863     LIS->removeAllRegUnitsForPhysReg(SB.SuperReg);  in restoreSGPR()
1885               ? SB.SuperReg  in spillEmergencySGPR()
1886               : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in spillEmergencySGPR()
1902         WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState);  in spillEmergencySGPR()
1920               ? SB.SuperReg  in spillEmergencySGPR()
1921               : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in spillEmergencySGPR()
1928         MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);  in spillEmergencySGPR()