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Searched refs:SuperClasses (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/utils/TableGen/
H A DAsmMatcherEmitter.cpp178 std::vector<ClassInfo*> SuperClasses; member
259 while (!Root->SuperClasses.empty()) in isRelatedTo()
260 Root = Root->SuperClasses.front(); in isRelatedTo()
294 while (!Root->SuperClasses.empty()) { in getTreeDepth()
296 Root = Root->SuperClasses.front(); in getTreeDepth()
303 while (!Root->SuperClasses.empty()) in findRoot()
304 Root = Root->SuperClasses.front(); in findRoot()
1379 CI->SuperClasses.push_back(SC); in buildOperandClasses()
2538 if (SuperClasses.empty()) in emitIsSubclass()
2551 if (SuperClasses.size() == 1) { in emitIsSubclass()
[all …]
H A DCodeGenRegisters.h300 SmallVector<CodeGenRegisterClass*, 4> SuperClasses; variable
421 return SuperClasses; in getSuperClasses()
H A DCodeGenRegisters.cpp836 assert(!SuperClasses.empty() && "Synthesized class without super class"); in inheritProperties()
839 CodeGenRegisterClass &Super = *SuperClasses.back(); in inheritProperties()
847 Allocatable = any_of(SuperClasses, [&](const CodeGenRegisterClass *S) { in inheritProperties()
1011 I->SuperClasses.push_back(&RC); in computeSubClasses()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h68 const sc_iterator SuperClasses; variable
178 return SuperClasses; in getSuperClasses()
184 return SuperClasses[0] != nullptr; in isASubClass()
/llvm-project-15.0.7/llvm/include/llvm/TableGen/
H A DRecord.h1568 SmallVector<std::pair<Record *, SMRange>, 0> SuperClasses; variable
1604 SuperClasses(O.SuperClasses), TrackedRecords(O.TrackedRecords), in Record()
1651 return SuperClasses; in getSuperClasses()
1717 for (const auto &SCPair : SuperClasses) in isSubClassOf()
1724 for (const auto &SCPair : SuperClasses) { in isSubClassOf()
1739 SuperClasses.push_back(std::make_pair(R, Range)); in addSuperClass()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstrInfo.td574 let SuperClasses = Supers;
583 let SuperClasses = Supers;
592 let SuperClasses = Supers;
602 let SuperClasses = Supers;
611 let SuperClasses = Supers;
620 let SuperClasses = Supers;
630 let SuperClasses = Supers;
711 let SuperClasses = [SImm16AsmOperandClass];
740 let SuperClasses = [ConstantSImm9AsmOperandClass];
1095 let SuperClasses = [MipsMemAsmOperand];
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H A DMicroMipsInstrInfo.td150 let SuperClasses = [MipsMemAsmOperand];
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrInfo.td387 let SuperClasses = [X86MemAsmOperand];
489 let SuperClasses = [X86AbsMemAsmOperand];
516 let SuperClasses = [X86Mem8AsmOperand];
535 let SuperClasses = [X86Mem8AsmOperand];
539 let SuperClasses = [X86Mem16AsmOperand];
543 let SuperClasses = [X86Mem32AsmOperand];
547 let SuperClasses = [X86Mem64AsmOperand];
554 let SuperClasses = [X86Mem8AsmOperand];
566 let SuperClasses = [X86Mem8AsmOperand];
582 let SuperClasses = [X86Mem8AsmOperand];
[all …]
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrInfo.td172 let SuperClasses = superClasses;
181 let RenderMethod = "addRegOperands", SuperClasses = [MxRegClass]in {
/llvm-project-15.0.7/clang/utils/TableGen/
H A DClangAttrEmitter.cpp3008 auto SuperClasses = R->getSuperClasses(); in findSuperClass() local
3009 for (signed i = 0, e = SuperClasses.size(); i != e; ++i) { in findSuperClass()
3010 auto SuperClass = findClassByRecord(SuperClasses[e - i - 1].first); in findSuperClass()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td137 let SuperClasses = [ShifterOperand];
143 let SuperClasses = [ShifterOperand];
151 let SuperClasses = [ShifterOperand];
163 let SuperClasses = [ShifterOperand];
175 let SuperClasses = [ShifterOperand];
180 let SuperClasses = [LogicalVecShifterOperand];
187 let SuperClasses = [ShifterOperand];
198 let SuperClasses = [ExtendOperand];
204 let SuperClasses = [ExtendOperand];
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTarget.td828 list<AsmOperandClass> SuperClasses = [];