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Searched refs:SrcVec (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp189 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
200 .addReg(SrcVec) in RebuildVector()
211 SrcVec = DstReg; in RebuildVector()
214 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec); in RebuildVector()
H A DAMDGPUInstructionSelector.cpp2906 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
2916 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
2919 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
2926 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
2929 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
2958 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
2959 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
2987 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
2988 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
2993 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
[all …]
H A DSIISelLowering.cpp3874 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst() local
3878 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg()); in emitIndirectDst()
3886 SrcVec->getReg(), in emitIndirectDst()
3897 .add(*SrcVec) in emitIndirectDst()
3916 .addReg(SrcVec->getReg()) in emitIndirectDst()
3926 .addReg(SrcVec->getReg()) in emitIndirectDst()
3943 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, Offset, in emitIndirectDst()
7084 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, in LowerINTRINSIC_WO_CHAIN() local
7087 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN()
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp390 Value *SrcVec = EI.getVectorOperand(); in visitExtractElementInst() local
392 if (Value *V = simplifyExtractElementInst(SrcVec, Index, in visitExtractElementInst()
436 if (auto *Phi = dyn_cast<PHINode>(SrcVec)) in visitExtractElementInst()
444 if (match(SrcVec, m_UnOp(UO)) && cheapToScalarize(SrcVec, Index)) { in visitExtractElementInst()
452 if (match(SrcVec, m_BinOp(BO)) && cheapToScalarize(SrcVec, Index)) { in visitExtractElementInst()
462 if (match(SrcVec, m_Cmp(Pred, m_Value(X), m_Value(Y))) && in visitExtractElementInst()
463 cheapToScalarize(SrcVec, Index)) { in visitExtractElementInst()
470 if (auto *I = dyn_cast<Instruction>(SrcVec)) { in visitExtractElementInst()
560 if (SrcVec->hasOneUse()) { in visitExtractElementInst()
576 if (V != SrcVec) { in visitExtractElementInst()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp444 Register SrcVec = Left; in matchINS() local
448 SrcVec = Right; in matchINS()
452 MatchInfo = std::make_tuple(DstVec, DstLane, SrcVec, SrcLane); in matchINS()
462 Register DstVec, SrcVec; in applyINS() local
464 std::tie(DstVec, DstLane, SrcVec, SrcLane) = MatchInfo; in applyINS()
466 auto Extract = Builder.buildExtractVectorElement(ScalarTy, SrcVec, SrcCst); in applyINS()
/llvm-project-15.0.7/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp1549 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
1561 SrcVec = Src; in executeBitCastInst()
1567 SrcVec.AggregateVal.push_back(Src); in executeBitCastInst()
1588 APInt::floatToBits(SrcVec.AggregateVal[i].FloatVal); in executeBitCastInst()
1593 APInt::doubleToBits(SrcVec.AggregateVal[i].DoubleVal); in executeBitCastInst()
1596 TempSrc.AggregateVal[i].IntVal = SrcVec.AggregateVal[i].IntVal; in executeBitCastInst()
/llvm-project-15.0.7/llvm/lib/IR/
H A DVerifier.cpp2978 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
2981 Check(SrcVec == DstVec, in visitUIToFPInst()
2988 if (SrcVec && DstVec) in visitUIToFPInst()
3001 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
3004 Check(SrcVec == DstVec, in visitSIToFPInst()
3011 if (SrcVec && DstVec) in visitSIToFPInst()
3024 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
3027 Check(SrcVec == DstVec, in visitFPToUIInst()
3033 if (SrcVec && DstVec) in visitFPToUIInst()
3049 Check(SrcVec == DstVec, in visitFPToSIInst()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp2729 Register SrcVec = MI.getOperand(1).getReg(); in bitcastExtractVectorElt() local
2731 LLT SrcVecTy = MRI.getType(SrcVec); in bitcastExtractVectorElt()
2869 Register SrcVec = MI.getOperand(1).getReg(); in bitcastInsertVectorElt() local
3946 Register SrcVec = MI.getOperand(1).getReg(); in fewerElementsVectorExtractInsertVectorElt() local
3960 LLT VecTy = MRI.getType(SrcVec); in fewerElementsVectorExtractInsertVectorElt()
3976 LLT GCDTy = extractGCDType(VecParts, VecTy, NarrowVecTy, SrcVec); in fewerElementsVectorExtractInsertVectorElt()
6567 Register SrcVec = MI.getOperand(1).getReg(); in lowerExtractInsertVectorElt() local
6574 LLT VecTy = MRI.getType(SrcVec); in lowerExtractInsertVectorElt()
6581 extractParts(SrcVec, EltTy, NumElts, SrcRegs); in lowerExtractInsertVectorElt()
6606 MIRBuilder.buildStore(SrcVec, StackTemp, PtrInfo, VecAlign); in lowerExtractInsertVectorElt()
[all …]
H A DCombinerHelper.cpp3918 Register SrcVec = MI.getOperand(1).getReg(); in matchExtractVecEltBuildVec() local
3919 LLT SrcTy = MRI.getType(SrcVec); in matchExtractVecEltBuildVec()
3930 getOpcodeDef(TargetOpcode::G_BUILD_VECTOR, SrcVec, MRI); in matchExtractVecEltBuildVec()
3932 BuildVecMI = getOpcodeDef(TargetOpcode::G_BUILD_VECTOR_TRUNC, SrcVec, MRI); in matchExtractVecEltBuildVec()
3942 if (!MRI.hasOneNonDBGUse(SrcVec) && in matchExtractVecEltBuildVec()
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIRBuilder.h918 CallInst *CreateExtractVector(Type *DstType, Value *SrcVec, Value *Idx,
921 {DstType, SrcVec->getType()}, {SrcVec, Idx}, nullptr,
926 CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec,
929 {DstType, SubVec->getType()}, {SrcVec, SubVec, Idx},
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCodeGenFunction.cpp2762 llvm::Value *CodeGenFunction::emitBoolVecConversion(llvm::Value *SrcVec, in emitBoolVecConversion() argument
2765 auto *SrcTy = cast<llvm::FixedVectorType>(SrcVec->getType()); in emitBoolVecConversion()
2768 return SrcVec; in emitBoolVecConversion()
2775 return Builder.CreateShuffleVector(SrcVec, ShuffleMask, Name); in emitBoolVecConversion()
H A DCodeGenFunction.h4661 llvm::Value *emitBoolVecConversion(llvm::Value *SrcVec,
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp10771 SrcVec = widenSubVector(VT, SrcVec, false, Subtarget, DAG, SDLoc(SrcVec)); in createVariablePermute()
10838 DAG.getVectorShuffle(VT, DL, SrcVec, SrcVec, {0, 0}), in createVariablePermute()
10839 DAG.getVectorShuffle(VT, DL, SrcVec, SrcVec, {1, 1}), in createVariablePermute()
10894 SrcVec = DAG.getBitcast(MVT::v8f32, SrcVec); in createVariablePermute()
10895 SDValue LoLo = DAG.getVectorShuffle(MVT::v8f32, DL, SrcVec, SrcVec, in createVariablePermute()
10897 SDValue HiHi = DAG.getVectorShuffle(MVT::v8f32, DL, SrcVec, SrcVec, in createVariablePermute()
10918 SrcVec = widenSubVector(WidenSrcVT, SrcVec, false, Subtarget, DAG, in createVariablePermute()
10928 SrcVec = DAG.getBitcast(MVT::v4f64, SrcVec); in createVariablePermute()
10979 SrcVec = DAG.getBitcast(ShuffleVT, SrcVec); in createVariablePermute()
11012 if (!SrcVec) in LowerBUILD_VECTORAsVariablePermute()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1980 auto GetConvertedLane = [](SDValue Op, unsigned &Opcode, SDValue &SrcVec, in LowerConvertLow()
2003 SrcVec = ExtractVector.getOperand(0); in LowerConvertLow()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp687 auto IsBuildFromExtracts = [this,&Values] (SDValue &SrcVec, in buildHvxVectorReg()
709 SrcVec = Vec; in buildHvxVectorReg()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp10578 SDValue SrcVec = V1; in LowerVECTOR_SHUFFLE() local
10581 SrcVec = V2; in LowerVECTOR_SHUFFLE()
10593 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV), in LowerVECTOR_SHUFFLE()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp14442 SDValue SrcVec = Ext1.getOperand(0); in DAGCombineBuildVector() local
14446 SrcVec, DAG.getIntPtrConstant(SubvecIdx, dl)); in DAGCombineBuildVector()