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Searched refs:ShiftBits (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.cpp99 unsigned ShiftBits = 32 - XCOFF::TracebackTable::WidthOfParamType; in getVecExtParmsType() local
110 XCOFF::TracebackTable::ParmTypeIsVectorCharBit >> ShiftBits; in getVecExtParmsType()
116 XCOFF::TracebackTable::ParmTypeIsVectorShortBit >> ShiftBits; in getVecExtParmsType()
122 XCOFF::TracebackTable::ParmTypeIsVectorIntBit >> ShiftBits; in getVecExtParmsType()
128 XCOFF::TracebackTable::ParmTypeIsVectorFloatBit >> ShiftBits; in getVecExtParmsType()
144 unsigned ShiftBits = 32 - XCOFF::TracebackTable::WidthOfParamType; in getParmsType() local
158 XCOFF::TracebackTable::ParmTypeIsFixedBits >> ShiftBits; in getParmsType()
170 XCOFF::TracebackTable::ParmTypeIsFloatingBits >> ShiftBits; in getParmsType()
177 XCOFF::TracebackTable::ParmTypeIsDoubleBits >> ShiftBits; in getParmsType()
187 XCOFF::TracebackTable::ParmTypeIsVectorBits >> ShiftBits; in getParmsType()
H A DPPCRegisterInfo.cpp994 unsigned ShiftBits = getEncodingValue(DestReg)*4; in lowerCRRestore() local
997 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) in lowerCRRestore()
1156 unsigned ShiftBits = getEncodingValue(DestReg); in lowerCRBitRestore() local
1161 .addImm(ShiftBits ? 32 - ShiftBits : 0) in lowerCRBitRestore()
1162 .addImm(ShiftBits) in lowerCRBitRestore()
1163 .addImm(ShiftBits); in lowerCRBitRestore()
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DBasicAliasAnalysis.cpp450 unsigned ShiftBits = Offset.getBitWidth() - IndexSize; in adjustToIndexSize() local
451 return (Offset << ShiftBits).ashr(ShiftBits); in adjustToIndexSize()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp4789 unsigned ShiftBits = AndRHSC.countTrailingZeros(); in SimplifySetCC() local
4790 if (!TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) { in SimplifySetCC()
4793 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
4794 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, ShValTy); in SimplifySetCC()
4806 unsigned ShiftBits; in SimplifySetCC() local
4810 ShiftBits = C1.countTrailingOnes(); in SimplifySetCC()
4814 ShiftBits = C1.countTrailingZeros(); in SimplifySetCC()
4816 NewC.lshrInPlace(ShiftBits); in SimplifySetCC()
4817 if (ShiftBits && NewC.getMinSignedBits() <= 64 && in SimplifySetCC()
4819 !TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) { in SimplifySetCC()
[all …]
H A DDAGCombiner.cpp5606 unsigned ShiftBits = CShift->getZExtValue(); in visitANDLike() local
5609 if (ShiftBits == 0) in visitANDLike()
5618 (ShiftBits + MaskBits <= Size / 2) && in visitANDLike()
5638 SDValue ShiftK = DAG.getConstant(ShiftBits, SL, ShiftVT); in visitANDLike()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4764 unsigned ShiftBits = countLeadingZeros(Mask); in getARMCmp() local
4765 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) { in getARMCmp()
4766 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32); in getARMCmp()
4768 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32); in getARMCmp()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp6771 SDValue ShiftBits = DAG.getTargetConstant(SubVecNumElems, dl, MVT::i8); in insert1BitVector() local
6774 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()
6775 Vec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()
6830 SDValue ShiftBits = DAG.getTargetConstant(NumElems - IdxVal, dl, MVT::i8); in insert1BitVector() local
6831 Vec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()
6832 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()