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Searched refs:ScaledReg (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp580 ScaledReg ? ScaledReg->getType() : in getType()
601 if (ScaledReg) in hasRegsUsedByUsesOtherThan()
1365 if (const SCEV *ScaledReg = F.ScaledReg) { in RateFormula() local
1549 if (F.ScaledReg) Key.push_back(F.ScaledReg); in HasFormulaWithSameRegs()
1573 if (F.ScaledReg) Key.push_back(F.ScaledReg); in InsertFormula()
1581 assert((!F.ScaledReg || !F.ScaledReg->isZero()) && in InsertFormula()
1612 if (F.ScaledReg) Regs.insert(F.ScaledReg); in RecomputeRegs()
2672 F.ScaledReg == OrigF.ScaledReg && in FindUseWithSimilarFormula()
4026 F.ScaledReg = SE.getMulExpr(F.ScaledReg, FactorS); in GenerateICmpZeroScales()
4928 if (const SCEV *ScaledReg = F.ScaledReg) { in NarrowSearchSpaceByDeletingCostlyFormulas() local
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DImplicitNullChecks.cpp380 const Register BaseReg = AddrMode.BaseReg, ScaledReg = AddrMode.ScaledReg; in isSuitableMemoryOp() local
385 if (BaseReg != PointerReg && ScaledReg != PointerReg) in isSuitableMemoryOp()
393 (ScaledReg && in isSuitableMemoryOp()
394 TRI->getRegSizeInBits(ScaledReg, MRI) != PointerRegSizeInBits)) in isSuitableMemoryOp()
453 if (CalculateDisplacementFromAddrMode(ScaledReg, AddrMode.Scale)) in isSuitableMemoryOp()
462 (ScaledReg && ScaledReg != PointerReg && !ScaledRegIsConstVal)) in isSuitableMemoryOp()
H A DCodeGenPrepare.cpp2449 Value *ScaledReg = nullptr; member
2478 if (ScaledReg && other.ScaledReg && in compare()
2479 ScaledReg->getType() != other.ScaledReg->getType()) in compare()
2494 if (ScaledReg != other.ScaledReg) in compare()
2526 return ScaledReg; in GetFieldAsValue()
2549 ScaledReg = V; in SetCombinedField()
2563 ScaledReg = V; in SetCombinedField()
5014 Value *BaseReg = AMAfter.BaseReg, *ScaledReg = AMAfter.ScaledReg; in isProfitableToFoldIntoAddressingMode() local
5020 if (valueAlreadyLiveAtInst(ScaledReg, AMBefore.BaseReg, AMBefore.ScaledReg)) in isProfitableToFoldIntoAddressingMode()
5021 ScaledReg = nullptr; in isProfitableToFoldIntoAddressingMode()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp2275 Register ScaledReg = ResultReg; in eliminateFrameIndex() local
2278 ScaledReg) in eliminateFrameIndex()
2288 MIB.addReg(ScaledReg, RegState::Kill); in eliminateFrameIndex()
2305 MIB.addReg(ScaledReg, RegState::Kill); in eliminateFrameIndex()
2321 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHR_B32), ScaledReg) in eliminateFrameIndex()
2324 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), ScaledReg) in eliminateFrameIndex()
2325 .addReg(ScaledReg, RegState::Kill) in eliminateFrameIndex()
2329 .addReg(ScaledReg, RegState::Kill); in eliminateFrameIndex()
2331 ResultReg = ScaledReg; in eliminateFrameIndex()
2335 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), ScaledReg) in eliminateFrameIndex()
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/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/X86/
H A Dlsr-filtering-scaledreg.ll22 ; Without filtering non-optimal formulae with the same ScaledReg and Scale, the strategy
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/
H A Dillegal-addr-modes.ll12 ; same ScaledReg and Scale."
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h87 Register ScaledReg; member
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp3718 AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg(); in getAddrModeFromMemoryOp()
3732 if (AM.ScaledReg != X86::NoRegister) { in verifyInstruction()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp2573 AM.ScaledReg = 0; in getAddrModeFromMemoryOp()