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Searched refs:SVT (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCSymbolXCOFF.h52 void setVisibilityType(XCOFF::VisibilityType SVT) { VisibilityType = SVT; }; in setVisibilityType() argument
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp952 MVT SVT = VT.getSimpleVT(); in getTypeConversion() local
954 MVT NVT = TransformToType[SVT.SimpleTy]; in getTypeConversion()
1412 MVT SVT = (MVT::SimpleValueType) nVT; in computeRegisterProperties() local
1416 SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) { in computeRegisterProperties()
1417 TransformToType[i] = SVT; in computeRegisterProperties()
1418 RegisterTypeForVT[i] = SVT; in computeRegisterProperties()
1434 MVT SVT = (MVT::SimpleValueType) nVT; in computeRegisterProperties() local
1435 if (SVT.getVectorElementType() == EltVT && in computeRegisterProperties()
1439 isTypeLegal(SVT)) { in computeRegisterProperties()
1440 TransformToType[i] = SVT; in computeRegisterProperties()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp203 Type *SVT = VT->getElementType(); in simplifyX86immShift() local
206 unsigned BitWidth = SVT->getPrimitiveSizeInBits(); in simplifyX86immShift()
216 Amt = Builder.CreateZExtOrTrunc(Amt, SVT); in simplifyX86immShift()
225 Amt = ConstantInt::get(SVT, BitWidth - 1); in simplifyX86immShift()
232 cast<VectorType>(AmtVT)->getElementType() == SVT && in simplifyX86immShift()
259 cast<VectorType>(AmtVT)->getElementType() == SVT && in simplifyX86immShift()
351 Type *SVT = VT->getElementType(); in simplifyX86varShift() local
353 int BitWidth = SVT->getIntegerBitWidth(); in simplifyX86varShift()
405 ConstantVec.push_back(UndefValue::get(SVT)); in simplifyX86varShift()
422 ShiftVecAmts.push_back(UndefValue::get(SVT)); in simplifyX86varShift()
[all …]
H A DX86ISelLowering.cpp6696 DstVT = MVT::getVectorVT(SVT, 512 / SVT.getSizeInBits()); in getAVX512Node()
22931 if (!SVT.isVector()) in LowerFP_EXTEND()
22968 if (SVT == MVT::f128 || (VT == MVT::f16 && SVT == MVT::f80)) in LowerFP_ROUND()
25429 if (SVT != MVT::i64 && SVT != MVT::i32 && SVT != MVT::i16) in LowerEXTEND_VECTOR_INREG()
44081 if (SVT != MVT::i64 && SVT != MVT::i32 && SVT != MVT::i16 && SVT != MVT::i8) in combineToExtendBoolVectorInReg()
48746 (SVT == MVT::i8 || SVT == MVT::i16) && in combineTruncateWithSat()
48773 (SVT == MVT::i32 || SVT == MVT::i16 || SVT == MVT::i8)) { in combineTruncateWithSat()
50252 if (SVT != MVT::i8 && SVT != MVT::i16 && SVT != MVT::i32) in combineVectorSignBitsTruncation()
50807 !(SVT == MVT::f32 || SVT == MVT::f64) || in getNegatedExpression()
51635 if (SVT != MVT::i8 && SVT != MVT::i16 && SVT != MVT::i32 && in combineExtSetcc()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DValueTypes.h41 constexpr EVT(MVT::SimpleValueType SVT) : V(SVT) {} in EVT()
H A DSelectionDAG.h1316 MachinePointerInfo PtrInfo, EVT SVT, Align Alignment,
1321 MachinePointerInfo PtrInfo, EVT SVT,
1325 return getTruncStore(Chain, dl, Val, Ptr, PtrInfo, SVT,
1326 Alignment.value_or(getEVTAlign(SVT)), MMOFlags,
1332 MachinePointerInfo PtrInfo, EVT SVT, unsigned Alignment,
1335 return getTruncStore(Chain, dl, Val, Ptr, PtrInfo, SVT,
1339 SDValue Ptr, EVT SVT, MachineMemOperand *MMO);
1391 MachinePointerInfo PtrInfo, EVT SVT, Align Alignment,
1395 SDValue Ptr, SDValue Mask, SDValue EVL, EVT SVT,
1459 EVT SVT, Align Alignment,
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp2799 EVT LegalSVT = SVT; in getSplatValue()
2801 if (!SVT.isInteger()) in getSplatValue()
2804 if (LegalSVT.bitsLT(SVT)) in getSplatValue()
4905 EVT SVT = VT.getScalarType(); in foldCONCAT_VECTORS() local
4920 SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT); in foldCONCAT_VECTORS()
4925 Op = DAG.getUNDEF(SVT); in foldCONCAT_VECTORS()
5753 if (LegalSVT != SVT) in FoldConstantArithmetic()
7954 if (VT == SVT) in getTruncStore()
7972 ID.AddInteger(SVT.getRawBits()); in getTruncStore()
8204 if (VT == SVT) in getTruncStoreVP()
[all …]
H A DLegalizeDAG.cpp306 EVT SVT = VT; in ExpandConstantFP() local
311 while (SVT != MVT::f32 && SVT != MVT::f16) { in ExpandConstantFP()
312 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); in ExpandConstantFP()
316 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
320 VT = SVT; in ExpandConstantFP()
3249 MVT SVT = Op.getSimpleValueType(); in ExpandNode() local
3250 if ((SVT == MVT::f64 || SVT == MVT::f80) && in ExpandNode()
4265 if (NVT.bitsGE(SVT)) in ConvertNodeToLibcall()
4294 EVT SVT = Op.getValueType(); in ConvertNodeToLibcall() local
4309 LC = Signed ? RTLIB::getFPTOSINT(SVT, NVT) in ConvertNodeToLibcall()
[all …]
H A DLegalizeFloatTypes.cpp771 EVT SVT = N->getOperand(IsStrict ? 1 : 0).getValueType(); in SoftenFloatRes_XINT_TO_FP() local
784 if (NVT.bitsGE(SVT)) in SoftenFloatRes_XINT_TO_FP()
795 CallOptions.setTypeListBeforeSoften(SVT, RVT, true); in SoftenFloatRes_XINT_TO_FP()
894 EVT SVT = Op.getValueType(); in SoftenFloatOp_FP_ROUND() local
903 RTLIB::Libcall LC = RTLIB::getFPROUND(SVT, FloatRVT); in SoftenFloatOp_FP_ROUND()
909 CallOptions.setTypeListBeforeSoften(SVT, RVT, true); in SoftenFloatOp_FP_ROUND()
969 EVT SVT = Op.getValueType(); in SoftenFloatOp_FP_TO_XINT() local
978 RTLIB::Libcall LC = findFPToIntLibcall(SVT, RVT, NVT, Signed); in SoftenFloatOp_FP_TO_XINT()
985 CallOptions.setTypeListBeforeSoften(SVT, RVT, true); in SoftenFloatOp_FP_TO_XINT()
H A DLegalizeIntegerTypes.cpp330 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType()); in PromoteIntRes_AtomicCmpSwap() local
335 if (!TLI.isTypeLegal(SVT)) in PromoteIntRes_AtomicCmpSwap()
336 SVT = NVT; in PromoteIntRes_AtomicCmpSwap()
647 EVT SVT = In.getValueType().getScalarType(); in PromoteIntRes_EXTRACT_VECTOR_ELT() local
648 if (SVT.bitsGE(NVT)) { in PromoteIntRes_EXTRACT_VECTOR_ELT()
830 EVT SVT = getSetCCResultType(VT); in PromoteIntRes_Overflow() local
1151 EVT SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC() local
1156 if (getTypeAction(SVT) == TargetLowering::TypePromoteInteger) { in PromoteIntRes_SETCC()
1159 SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
1162 SVT = NVT; in PromoteIntRes_SETCC()
[all …]
H A DDAGCombiner.cpp11365 EVT SVT = VT.getScalarType(); in tryToFoldExtendOfConstant() local
11384 Elts.push_back(IsZext ? DAG.getConstant(0, DL, SVT) : DAG.getUNDEF(SVT)); in tryToFoldExtendOfConstant()
11870 if (SVT != N0.getValueType()) { in foldSextSetcc()
13298 EVT SVT = VT.getScalarType(); in visitTRUNCATE() local
21184 EVT SVT = VT.getScalarType(); in visitCONCAT_VECTORS() local
21186 EVT MinVT = SVT; in visitCONCAT_VECTORS()
21187 if (!SVT.isFloatingPoint()) { in visitCONCAT_VECTORS()
22066 EVT SVT = VT.getScalarType(); in combineShuffleOfScalars() local
22067 if (SVT.isInteger()) in combineShuffleOfScalars()
22069 SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT); in combineShuffleOfScalars()
[all …]
H A DTargetLowering.cpp5685 EVT SVT = VT.getScalarType(); in BuildExactSDIV() local
5775 EVT SVT = VT.getScalarType(); in BuildSDIV() local
5923 EVT SVT = VT.getScalarType(); in BuildUDIV() local
5986 dl, SVT)); in BuildUDIV()
6146 EVT SVT = VT.getScalarType(); in prepareUREMEqFold() local
6236 PAmts.push_back(DAG.getConstant(P, DL, SVT)); in prepareUREMEqFold()
6239 QAmts.push_back(DAG.getConstant(Q, DL, SVT)); in prepareUREMEqFold()
6395 EVT SVT = VT.getScalarType(); in prepareSREMEqFold() local
6489 PAmts.push_back(DAG.getConstant(P, DL, SVT)); in prepareSREMEqFold()
6490 AAmts.push_back(DAG.getConstant(A, DL, SVT)); in prepareSREMEqFold()
[all …]
H A DLegalizeVectorTypes.cpp6054 EVT SVT = getSetCCResultType(InOp0.getValueType()); in WidenVecOp_SETCC() local
6057 SVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, in WidenVecOp_SETCC()
6058 SVT.getVectorElementCount()); in WidenVecOp_SETCC()
6061 SVT, InOp0, InOp1, N->getOperand(2)); in WidenVecOp_SETCC()
6065 SVT.getVectorElementType(), in WidenVecOp_SETCC()
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DMachineValueType.h332 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {} in MVT() argument
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1213 EVT SVT = (UW == 32 || UW == 64) ? MVT::getIntegerVT(UW) : UVT; in ppHoistZextI1() local
1214 SDValue Sel = DAG.getNode(ISD::SELECT, dl, SVT, OpI1, in ppHoistZextI1()
1215 DAG.getBitcast(SVT, If1), in ppHoistZextI1()
1216 DAG.getBitcast(SVT, If0)); in ppHoistZextI1()
H A DHexagonISelLowering.cpp3563 MVT SVT = VT.getSimpleVT(); in allowsMemoryAccess() local
3564 if (Subtarget.isHVXVectorType(SVT, true)) in allowsMemoryAccess()
3565 return allowsHvxMemoryAccess(SVT, Flags, Fast); in allowsMemoryAccess()
3573 MVT SVT = VT.getSimpleVT(); in allowsMisalignedMemoryAccesses() local
3574 if (Subtarget.isHVXVectorType(SVT, true)) in allowsMisalignedMemoryAccesses()
3575 return allowsHvxMisalignedMemoryAccesses(SVT, Flags, Fast); in allowsMisalignedMemoryAccesses()
H A DHexagonISelDAGToDAGHVX.cpp1061 MVT::SimpleValueType SVT = MVT::SimpleValueType(R.OpN & OpRef::Index); in materialize() local
1062 Ops.push_back(ISel.selectUndef(dl, MVT(SVT))); in materialize()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2617 MVT SVT = VT.getVectorElementType(); in lowerVECTOR_SHUFFLE() local
2635 Offset *= SVT.getStoreSize(); in lowerVECTOR_SHUFFLE()
2640 if (SVT.isInteger() && SVT.bitsGT(XLenVT)) { in lowerVECTOR_SHUFFLE()
2651 ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, SVT, in lowerVECTOR_SHUFFLE()
2653 Ld->getMemOperand(), Offset, SVT.getStoreSize())); in lowerVECTOR_SHUFFLE()
2661 if (SVT.isFloatingPoint()) in lowerVECTOR_SHUFFLE()
2662 V = DAG.getLoad(SVT, DL, Ld->getChain(), NewAddr, in lowerVECTOR_SHUFFLE()
2668 Ld->getPointerInfo().getWithOffset(Offset), SVT, in lowerVECTOR_SHUFFLE()
2945 MVT SVT = VT.getSimpleVT(); in isShuffleMaskLegal() local
2950 isInterleaveShuffle(M, SVT, SwapSources, Subtarget); in isShuffleMaskLegal()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp6810 static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT, in getRegClassForSVT() argument
6814 assert((IsPPC64 || SVT != MVT::i64) && in getRegClassForSVT()
6817 switch (SVT) { in getRegClassForSVT()
7001 MVT::SimpleValueType SVT = VA.getLocVT().SimpleTy; in LowerFormalArguments_AIX() local
7003 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
7142 MVT::SimpleValueType SVT = ValVT.SimpleTy; in LowerFormalArguments_AIX() local
7145 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
11254 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), in ReplaceNodeResults() local
11256 SDVTList VTs = DAG.getVTList(SVT, MVT::Other); in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp419 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; in allowsMisalignedMemoryAccesses() local
431 switch (SVT) { in allowsMisalignedMemoryAccesses()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DGlobalISelEmitter.cpp203 static Optional<LLTCodeGen> MVTToLLT(MVT::SimpleValueType SVT) { in MVTToLLT() argument
204 MVT VT(SVT); in MVTToLLT()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp11676 MVT SVT = Node->getValueType(0).getVectorElementType().getSimpleVT(); in adjustWritemask() local
11679 SVT : MVT::getVectorVT(SVT, NewChannels == 3 ? 4 : in adjustWritemask()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp8670 EVT SVT = VT.getScalarType() == MVT::i8 || VT.getScalarType() == MVT::i16 in LowerVECTOR_SHUFFLEUsingOneOff() local
8674 ISD::EXTRACT_VECTOR_ELT, dl, SVT, in LowerVECTOR_SHUFFLEUsingOneOff()
20376 const SDNode *N, MVT::SimpleValueType SVT) { in getDivRemLibcall() argument
20383 switch (SVT) { in getDivRemLibcall()