Home
last modified time | relevance | path

Searched refs:STRICT_LRINT (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h432 STRICT_LRINT, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp375 case ISD::STRICT_LRINT: return "strict_lrint"; in getOperationName()
H A DLegalizeDAG.cpp1015 case ISD::STRICT_LRINT: in LegalizeOp()
3889 case ISD::STRICT_LRINT: in ExpandNode()
4170 case ISD::STRICT_LRINT: in ConvertNodeToLibcall()
H A DSelectionDAGISel.cpp1132 case ISD::STRICT_LRINT: in DoInstructionSelection()
H A DLegalizeFloatTypes.cpp851 case ISD::STRICT_LRINT: in SoftenFloatOperand()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp535 Opcode = ISD::STRICT_LRINT; in mightUseCTR()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td547 def strict_lrint : SDNode<"ISD::STRICT_LRINT",
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp622 for (auto Op : {ISD::STRICT_LROUND, ISD::STRICT_LLROUND, ISD::STRICT_LRINT, in AArch64TargetLowering()
687 ISD::STRICT_LLROUND, ISD::STRICT_LRINT, ISD::STRICT_LLRINT}) { in AArch64TargetLowering()
5615 case ISD::STRICT_LRINT: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp305 ISD::STRICT_LRINT, ISD::STRICT_LLRINT, ISD::STRICT_LROUND, in RISCVTargetLowering()