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Searched refs:SSHLSAT (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-shift-of-shifted-logic-shlsat.mir226 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
228 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSHLSAT]], [[SSHLSAT1]]
255 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
257 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSHLSAT]], [[SSHLSAT1]]
285 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
287 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSHLSAT]], [[SSHLSAT1]]
315 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
317 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SSHLSAT]], [[SSHLSAT1]]
346 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SSHLSAT]], [[SSHLSAT1]]
376 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SSHLSAT]], [[SSHLSAT1]]
[all …]
H A Dcombine-shift-imm-chain-shlsat.mir16 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C]](s32)
17 ; CHECK-NEXT: $vgpr0 = COPY [[SSHLSAT]](s32)
39 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C]](s32)
40 …-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[SSHLSAT]](s32)
69 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C]](s32)
70 ; CHECK-NEXT: $vgpr0 = COPY [[SSHLSAT]](s32)
96 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s64) = G_SSHLSAT [[MV]], [[C]](s64)
97 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSHLSAT]](s64)
H A Dirtranslator-sat.ll388 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s16) = G_SSHLSAT [[TRUNC]], [[TRUNC1]](s16)
389 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SSHLSAT]](s16)
404 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[COPY1]](s32)
405 ; CHECK-NEXT: $vgpr0 = COPY [[SSHLSAT]](s32)
423 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s64) = G_SSHLSAT [[MV]], [[MV1]](s64)
424 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSHLSAT]](s64)
444 …; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(<2 x s32>) = G_SSHLSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]](<…
445 …; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSHLSAT]](<2 x …
H A Dcombine-shift-imm-chain-illegal-types.mir222 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s44) = G_SSHLSAT [[TRUNC]], [[C]](s44)
223 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SSHLSAT]](s44)
261 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s55) = G_SSHLSAT [[TRUNC]], [[C]](s55)
262 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SSHLSAT]](s55)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h359 SSHLSAT, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp325 case ISD::SSHLSAT: return "sshlsat"; in getOperationName()
H A DLegalizeVectorOps.cpp408 case ISD::SSHLSAT: in LegalizeOp()
H A DLegalizeIntegerTypes.cpp197 case ISD::SSHLSAT: in PromoteIntegerResult()
863 bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT; in PromoteIntRes_ADDSUBSHLSAT()
899 case ISD::SSHLSAT: in PromoteIntRes_ADDSUBSHLSAT()
2525 case ISD::SSHLSAT: in ExpandIntegerResult()
H A DLegalizeVectorTypes.cpp136 case ISD::SSHLSAT: in ScalarizeVectorResult()
1094 case ISD::SSHLSAT: in SplitVectorResult()
3719 case ISD::SSHLSAT: in WidenVectorResult()
H A DLegalizeDAG.cpp1143 case ISD::SSHLSAT: in LegalizeOp()
3421 case ISD::SSHLSAT: in ExpandNode()
H A DTargetLowering.cpp8948 bool IsSigned = Opcode == ISD::SSHLSAT; in expandShlSat()
8954 assert((Node->getOpcode() == ISD::SSHLSAT || in expandShlSat()
H A DDAGCombiner.cpp1726 case ISD::SSHLSAT: in visit()
9829 if (N->getOpcode() == ISD::SSHLSAT && N1C && in visitSHLSAT()
H A DSelectionDAG.cpp5453 case ISD::SSHLSAT: return C1.sshl_sat(C2); in FoldValue()
H A DSelectionDAGBuilder.cpp6548 setValue(&I, DAG.getNode(ISD::SSHLSAT, sdl, Op1.getValueType(), Op1, Op2)); in visitIntrinsicCall()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp804 ISD::SSHLSAT, ISD::USHLSAT, in initActions()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td426 def sshlsat : SDNode<"ISD::SSHLSAT" , SDTIntBinOp>;