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Searched refs:SPR (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrVFP.td2036 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2060 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
2077 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2101 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
2117 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2169 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2210 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2234 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
2262 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2314 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
[all …]
H A DARMInstrCDE.td487 def cde_vcx_s_regs : CDE_VCX_RegisterOperandsTemplate<SPR>;
551 (f32 (CDE_VCX1A_fpsp p_imm:$coproc, SPR:$acc, imm_11b:$imm))>;
557 def : Pat<(f32 (int_arm_cde_vcx2 timm:$coproc, (f32 SPR:$n), timm:$imm)),
558 (f32 (CDE_VCX2_fpsp p_imm:$coproc, SPR:$n, imm_6b:$imm))>;
559 def : Pat<(f32 (int_arm_cde_vcx2a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n),
561 (f32 (CDE_VCX2A_fpsp p_imm:$coproc, SPR:$acc, SPR:$n, imm_6b:$imm))>;
568 def : Pat<(f32 (int_arm_cde_vcx3 timm:$coproc, (f32 SPR:$n), (f32 SPR:$m),
570 (f32 (CDE_VCX3_fpsp p_imm:$coproc, (f32 SPR:$n), (f32 SPR:$m),
572 def : Pat<(f32 (int_arm_cde_vcx3a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n),
573 (f32 SPR:$m), timm:$imm)),
[all …]
H A DARMRegisterInfo.td412 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
413 let AltOrders = [(add (decimate SPR, 2), SPR),
414 (add (decimate SPR, 4),
415 (decimate SPR, 2),
416 (decimate (rotl SPR, 1), 4),
417 (decimate (rotl SPR, 1), 2))];
425 let AltOrders = [(add (decimate HPR, 2), SPR),
436 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
461 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
466 // 32-bit SPR subregs).
[all …]
H A DARMRegisterBanks.td13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
H A DARMInstrNEON.td5264 def VFMALD : N3VCP8F16Q0<"vfmal", DPR, SPR, SPR, 0b00, 0b10, 1>;
5265 def VFMSLD : N3VCP8F16Q0<"vfmsl", DPR, SPR, SPR, 0b01, 0b10, 1>;
6732 def : Pat<(v2f32 (ARMvdup (f32 SPR:$src))),
6735 def : Pat<(v4f32 (ARMvdup (f32 SPR:$src))),
7389 : NEONFPPat<(f32 (OpNode SPR:$a)),
7397 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
7402 SPR:$a, ssub_0),
7419 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
7424 SPR:$acc, ssub_0),
7427 SPR:$a, ssub_0),
[all …]
H A DARMInstrMVE.td881 f32, SPR>;
1904 (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG MQPR:$src, (SSubReg_f32_reg imm:$lane))), SPR)>;
1905 def : Pat<(insertelt (v4f32 MQPR:$src1), (f32 SPR:$src2), imm:$lane),
1906 …(INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS MQPR:$src1, MQPR)), SPR:$src2, (SSubReg_f32_reg imm:$lane)…
1914 (COPY_TO_REGCLASS HPR:$src2, SPR)),
1928 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
1929 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dperm.avx2-false-deps.ll23 ; ENABLE-SPR-LABEL: permd:
24 ; ENABLE-SPR: # %bb.0:
27 ; ENABLE-SPR-NEXT: #APP
28 ; ENABLE-SPR-NEXT: nop
34 ; ENABLE-SPR-NEXT: retq
50 ; DISABLE-SPR-LABEL: permd:
54 ; DISABLE-SPR-NEXT: #APP
55 ; DISABLE-SPR-NEXT: nop
84 ; ENABLE-SPR-NEXT: #APP
85 ; ENABLE-SPR-NEXT: nop
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td51 // SPR - One of the 32-bit special-purpose registers
52 class SPR<bits<10> num, string n> : PPCReg<n> {
246 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
248 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
251 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
252 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
255 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
258 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
260 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
263 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
H A DPPCInstrFormats.td1593 bits<10> SPR;
1596 let Inst{11} = SPR{4};
1597 let Inst{12} = SPR{3};
1598 let Inst{13} = SPR{2};
1599 let Inst{14} = SPR{1};
1600 let Inst{15} = SPR{0};
1601 let Inst{16} = SPR{9};
1602 let Inst{17} = SPR{8};
1603 let Inst{18} = SPR{7};
1613 let SPR = spr;
[all …]
H A DPPCInstr64Bit.td557 def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR),
558 "mfspr $RT, $SPR", IIC_SprMFSPR>;
559 def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT),
560 "mtspr $SPR, $RT", IIC_SprMTSPR>;
564 // 64-bit SPR manipulation instrs.
1967 def : Pat<(i64 (int_ppc_mfspr timm:$SPR)),
1968 (MFSPR8 $SPR)>;
1969 def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT),
1970 (MTSPR8 $SPR, $RT)>;
H A DPPCInstrInfo.td2514 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2515 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2517 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2519 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2520 "mftb $RT, $SPR", IIC_SprMFTB>;
2523 "mfpmr $RT, $SPR", IIC_SprMFPMR>;
2526 "mtpmr $SPR, $RT", IIC_SprMTPMR>;
5105 def : Pat<(i32 (int_ppc_mfspr timm:$SPR)),
5106 (MFSPR $SPR)>;
5107 def : Pat<(int_ppc_mtspr timm:$SPR, gprc:$RT),
[all …]
H A DPPC.td220 "Target supports move to SPR with branch fusion",
H A DP9InstrResources.td934 (instregex "MF(SPR|CTR|LR)(8)?$"),
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dinlineasm-X-allocation.ll5 ; Using this mechanism, we want to test toggling allocating GPR or SPR registers
H A Dvdup.ll479 ; Check that an SPR splat produces a vdup.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/GlobalISel/
H A Darm-select-copy_to_regclass-of-fptosi.mir8 # G_FPTOSI selects to a (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR), where
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86PartialReduction.cpp236 auto SPR = matchSelectPattern(SI, LHS, RHS); in trySADReplacement() local
237 if (SPR.Flavor != SPF_ABS) in trySADReplacement()
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DLazyValueInfo.cpp826 SelectPatternResult SPR = matchSelectPattern(SI, LHS, RHS); in solveBlockValueSelect() local
829 if (SelectPatternResult::isMinOrMax(SPR.Flavor) && in solveBlockValueSelect()
833 switch (SPR.Flavor) { in solveBlockValueSelect()
851 if (SPR.Flavor == SPF_ABS) { in solveBlockValueSelect()
860 if (SPR.Flavor == SPF_NABS) { in solveBlockValueSelect()
H A DValueTracking.cpp5974 SelectPatternResult SPR = matchClamp(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal); in matchMinMax() local
5975 if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN) in matchMinMax()
5976 return SPR; in matchMinMax()
5978 SPR = matchMinMaxOfMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal, Depth); in matchMinMax()
5979 if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN) in matchMinMax()
5980 return SPR; in matchMinMax()
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineSelect.cpp2951 SelectPatternResult SPR = matchSelectPattern(&SI, LHS, RHS, &CastOp); in visitSelectInst() local
2952 auto SPF = SPR.Flavor; in visitSelectInst()
2977 CmpInst::Predicate MinMaxPred = getMinMaxPred(SPF, SPR.Ordered); in visitSelectInst()
H A DInstCombineCompares.cpp6192 SelectPatternResult SPR = matchSelectPattern(SI, A, B); in visitICmpInst() local
6193 if (SPR.Flavor != SPF_UNKNOWN) in visitICmpInst()
6819 SelectPatternResult SPR = matchSelectPattern(SI, A, B); in visitFCmpInst() local
6820 if (SPR.Flavor != SPF_UNKNOWN) in visitFCmpInst()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp3299 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS); in visitSelect() local
3301 switch (SPR.Flavor) { in visitSelect()
3307 switch (SPR.NaNBehavior) { in visitSelect()
3324 switch (SPR.NaNBehavior) { in visitSelect()