Lines Matching refs:SPR
159 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
161 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]>,
194 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
196 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]>,
412 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
414 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>,
437 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
439 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>,
462 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
464 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>,
483 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
485 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>,
506 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
508 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>,
531 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
533 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
560 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
562 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
580 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
581 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
591 (outs), (ins SPR:$Sd, SPR:$Sm),
593 [(arm_cmpfpe SPR:$Sd, SPR:$Sm)]> {
610 (outs), (ins SPR:$Sd, SPR:$Sm),
612 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
634 (outs SPR:$Sd), (ins SPR:$Sm),
636 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
657 (outs), (ins SPR:$Sd),
659 [(arm_cmpfpe0 SPR:$Sd)]> {
685 (outs), (ins SPR:$Sd),
687 [(arm_cmpfp0 SPR:$Sd)]> {
706 (outs DPR:$Dd), (ins SPR:$Sm),
708 [(set DPR:$Dd, (fpextend SPR:$Sm))]>,
725 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
727 [(set SPR:$Sd, (fpround DPR:$Dm))]>,
751 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
758 (VCVTBHS (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>;
760 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
763 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
769 def : FP16Pat<(f16 (fpround SPR:$Sm)),
770 (COPY_TO_REGCLASS (VCVTBSH (IMPLICIT_DEF), SPR:$Sm), HPR)>;
771 def : FP16Pat<(fp_to_f16 SPR:$a),
772 (i32 (COPY_TO_REGCLASS (VCVTBSH (IMPLICIT_DEF), SPR:$a), GPR))>;
773 def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane),
776 SPR:$src2),
778 def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane),
781 SPR:$src2),
785 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
799 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
805 def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane),
808 SPR:$src2),
810 def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane),
813 SPR:$src2),
817 (outs DPR:$Dd), (ins SPR:$Sm),
833 (VCVTBHD (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>,
836 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>,
840 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm),
865 (outs DPR:$Dd), (ins SPR:$Sm),
879 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm),
899 (outs SPR:$Sd), (ins HPR:$Sm),
907 (outs SPR:$Sd), (ins HPR:$Sm),
915 (outs SPR:$Sd), (ins SPR:$Sm),
923 (outs SPR:$Sd), (ins SPR:$Sm),
931 (outs SPR:$Sd), (ins DPR:$Dm),
946 (outs SPR:$Sd), (ins DPR:$Dm),
973 def : Pat<(i32 (fp_to_sint (node SPR:$a))),
975 (!cast<Instruction>(NAME#"SS") SPR:$a),
977 def : Pat<(i32 (fp_to_uint (node SPR:$a))),
979 (!cast<Instruction>(NAME#"US") SPR:$a),
1005 (outs SPR:$Sd), (ins SPR:$Sm),
1007 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
1029 (outs SPR:$Sd), (ins SPR:$Sm),
1031 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
1046 (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
1049 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
1072 (outs SPR:$Sd), (ins SPR:$Sm),
1074 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
1091 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>,
1110 (outs SPR:$Sd), (ins SPR:$Sm),
1112 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>,
1128 (outs SPR:$Sd), (ins SPR:$Sm),
1135 (outs SPR:$Sd), (ins SPR:$Sm),
1140 (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
1155 (outs GPR:$Rt), (ins SPR:$Sn),
1157 [(set GPR:$Rt, (bitconvert SPR:$Sn))]>,
1179 (outs SPR:$Sn), (ins GPR:$Rt),
1181 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
1234 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
1258 // FMDHR: GPR -> SPR
1259 // FMDLR: GPR -> SPR
1307 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
1381 // FMRDH: SPR -> GPR
1382 // FMRDL: SPR -> GPR
1383 // FMRRS: SPR -> GPR
1384 // FMRX: SPR system reg -> GPR
1385 // FMSRR: GPR -> SPR
1450 (outs DPR:$Dd), (ins SPR:$Sm),
1459 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1466 (outs SPR:$Sd),(ins SPR:$Sm),
1478 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1484 (outs HPR:$Sd), (ins SPR:$Sm),
1493 (VSITOH (COPY_TO_REGCLASS GPR:$a, SPR))>;
1496 (outs DPR:$Dd), (ins SPR:$Sm),
1505 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1512 (outs SPR:$Sd), (ins SPR:$Sm),
1524 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1530 (outs HPR:$Sd), (ins SPR:$Sm),
1539 (VUITOH (COPY_TO_REGCLASS GPR:$a, SPR))>;
1604 (outs SPR:$Sd), (ins DPR:$Dm),
1624 (outs SPR:$Sd), (ins SPR:$Sm),
1635 def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
1636 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
1637 def : VFPPat<(i32 (fp_to_sint_sat SPR:$a, i32)),
1638 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
1640 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))),
1642 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
1643 def : VFPPat<(alignedstore32 (i32 (fp_to_sint_sat (f32 SPR:$a), i32)),
1645 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
1648 (outs SPR:$Sd), (ins HPR:$Sm),
1662 (outs SPR:$Sd), (ins DPR:$Dm),
1682 (outs SPR:$Sd), (ins SPR:$Sm),
1693 def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
1694 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
1695 def : VFPPat<(i32 (fp_to_uint_sat SPR:$a, i32)),
1696 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
1698 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))),
1700 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
1701 def : VFPPat<(alignedstore32 (i32 (fp_to_uint_sat (f32 SPR:$a), i32)),
1703 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
1706 (outs SPR:$Sd), (ins HPR:$Sm),
1722 (outs SPR:$Sd), (ins DPR:$Dm),
1724 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>,
1730 (outs SPR:$Sd), (ins SPR:$Sm),
1732 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]>,
1738 (outs SPR:$Sd), (ins SPR:$Sm),
1747 (outs SPR:$Sd), (ins DPR:$Dm),
1749 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>,
1755 (outs SPR:$Sd), (ins SPR:$Sm),
1757 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]>,
1763 (outs SPR:$Sd), (ins SPR:$Sm),
1774 (outs SPR:$Sd), (ins DPR:$Dm),
1822 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1828 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1834 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1840 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1848 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1857 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1866 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1875 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1908 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1914 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1920 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1926 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1934 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1943 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1952 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1961 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1993 : VFPAI<(outs SPR:$Sd), (ins SPR:$dst, SPR:$Sm),
2036 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2038 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
2039 SPR:$Sdin))]>,
2059 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
2060 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
2077 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2079 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2080 SPR:$Sdin))]>,
2100 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
2101 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
2117 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2119 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2120 SPR:$Sdin))]>,
2141 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
2142 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
2152 def : Pat<(fsub_mlx (fneg SPR:$dstin), (fmul_su SPR:$a, SPR:$b)),
2153 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
2169 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2171 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
2190 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
2191 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
2210 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2212 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
2213 SPR:$Sdin))]>,
2233 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
2234 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
2245 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
2246 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2262 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2264 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2265 SPR:$Sdin))]>,
2285 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
2286 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
2297 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
2298 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2314 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2316 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2317 SPR:$Sdin))]>,
2337 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
2338 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
2346 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
2347 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2356 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
2357 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2373 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2375 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
2394 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
2395 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
2404 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
2405 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2414 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
2415 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2432 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
2434 [(set (f32 SPR:$Sd),
2435 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
2626 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
2629 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
2666 (f32 (COPY_TO_REGCLASS (f16 (FCONSTH (vfp_f32f16imm_xform (f32 $imm)))), SPR))> {
2719 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
2724 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2728 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2733 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
2738 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2740 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2748 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
2750 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
2752 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
2754 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2756 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2758 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2768 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
2779 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;