| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 644 ReplaceNode(Node, SLLI); in Select() 674 ReplaceNode(Node, SLLI); in Select() 702 SDNode *SLLI = in Select() local 733 SDNode *SLLI = in Select() local 877 SDNode *SLLI = in Select() local 889 SDNode *SLLI = in Select() local 906 SDNode *SLLI = in Select() local 917 SDNode *SLLI = in Select() local 983 SDNode *SLLI = in Select() local 2182 case RISCV::SLLI: in hasAllNBitUsers() [all …]
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| H A D | RISCVSExtWRemoval.cpp | 128 case RISCV::SLLI: in isAllUsesReadW() 274 case RISCV::SLLI: in isSignExtendingOpW() 418 case RISCV::SLLI: in getWOp()
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| H A D | RISCVInstrInfoM.td | 115 (MULHU (SLLI GPR:$rs1, 32), (SLLI GPR:$rs2, 32))>;
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| H A D | RISCVRegisterInfo.cpp | 282 BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL) in eliminateFrameIndex()
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| H A D | RISCVInstrInfo.cpp | 1856 BuildMI(MBB, II, DL, get(RISCV::SLLI), VL) in getVLENFactoredAmount() 1880 BuildMI(MBB, II, DL, get(RISCV::SLLI), VL) in getVLENFactoredAmount() 1891 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) in getVLENFactoredAmount() 1902 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) in getVLENFactoredAmount()
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| H A D | RISCVInstrInfo.td | 639 def SLLI : Shift_ri<0b00000, 0b001, "slli">; 992 (SLLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>; 1187 def : PatGprUimmLog2XLen<shl, SLLI>; 1193 (SLLI (SRLI $rs, LeadingOnesMask:$mask), LeadingOnesMask:$mask)>; 1195 (SRLI (SLLI $rs, TrailingOnesMask:$mask), TrailingOnesMask:$mask)>; 1572 def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (SRLI (SLLI GPR:$rs1, 32), 32)>; 1577 (SRLI (SLLI GPR:$rs1, 32), (ImmSubFrom32 uimm5:$shamt))>;
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| H A D | RISCVInstrInfoZb.td | 1137 (SLLI (SH1ADD GPR:$r, GPR:$r), 1140 (SLLI (SH2ADD GPR:$r, GPR:$r), 1143 (SLLI (SH3ADD GPR:$r, GPR:$r),
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| H A D | RISCVFrameLowering.cpp | 575 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg) in emitPrologue()
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| H A D | RISCVInstrInfoC.td | 854 def : CompressPat<(SLLI GPRNoX0:$rs1, GPRNoX0:$rs1, uimmlog2xlennonzero:$imm),
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| /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/ |
| H A D | pass-fast-math-flags-sdnode.ll | 15 ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 32 16 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gprnox0 = SRLI killed [[SLLI]], 32
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| H A D | get-vlen-debugloc.mir | 31 ; CHECK-NEXT: $x10 = frame-setup SLLI killed $x10, 1 36 ; CHECK-NEXT: $x10 = frame-destroy SLLI killed $x10, 1
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| H A D | zvlsseg-spill.mir | 27 ; CHECK-NEXT: $x12 = frame-setup SLLI killed $x12, 3 39 ; CHECK-NEXT: $x10 = frame-destroy SLLI killed $x10, 3
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| H A D | addi-scalable-offset.mir | 41 ; CHECK-NEXT: $x12 = frame-setup SLLI killed $x12, 1 46 ; CHECK-NEXT: $x11 = SLLI killed $x11, 1
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| H A D | wrong-stack-offset-for-rvv-object.mir | 158 ; CHECK-NEXT: $x10 = frame-setup SLLI killed $x10, 1 163 ; CHECK-NEXT: $x10 = SLLI killed $x10, 1 167 ; CHECK-NEXT: $x10 = SLLI killed $x10, 1
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| H A D | emergency-slot.mir | 128 ; CHECK-NEXT: renamable $x13 = SLLI renamable $x11, 3 204 renamable $x13 = SLLI renamable $x11, 3
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| H A D | vmv-copy.mir | 200 ; CHECK-NEXT: $x12 = SLLI $x12, 1 206 $x12 = SLLI $x12, 1
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 24 case RISCV::SLLI: in getInstSeqCost() 150 Res.push_back(RISCVMatInt::Inst(RISCV::SLLI, ShiftAmount)); in generateInstSeqImpl() 188 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::SLLI, TrailingZeros)); in generateInstSeq() 412 case RISCV::SLLI: in getOpndKind()
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| /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/ |
| H A D | and.ll | 9 ; with the remainder zero, we can replace it with SLLI + SLRI 75 ; with the remainder zero, we can replace it with SRLI + SLLI.
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| H A D | imm.ll | 225 ; This can be materialized with ADDI+SLLI, improving compressibility. 931 ; This constant can be materialized for RV64 with ADDI+SLLI+ADDI+ADDI.
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsScheduleP5600.td | 441 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>;
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| H A D | MipsScheduleGeneric.td | 1562 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>;
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 2471 emitToStreamer(Out, MCInstBuilder(RISCV::SLLI) in emitPseudoExtend()
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