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Searched refs:SLLI (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp644 ReplaceNode(Node, SLLI); in Select()
674 ReplaceNode(Node, SLLI); in Select()
702 SDNode *SLLI = in Select() local
733 SDNode *SLLI = in Select() local
877 SDNode *SLLI = in Select() local
889 SDNode *SLLI = in Select() local
906 SDNode *SLLI = in Select() local
917 SDNode *SLLI = in Select() local
983 SDNode *SLLI = in Select() local
2182 case RISCV::SLLI: in hasAllNBitUsers()
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H A DRISCVSExtWRemoval.cpp128 case RISCV::SLLI: in isAllUsesReadW()
274 case RISCV::SLLI: in isSignExtendingOpW()
418 case RISCV::SLLI: in getWOp()
H A DRISCVInstrInfoM.td115 (MULHU (SLLI GPR:$rs1, 32), (SLLI GPR:$rs2, 32))>;
H A DRISCVRegisterInfo.cpp282 BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL) in eliminateFrameIndex()
H A DRISCVInstrInfo.cpp1856 BuildMI(MBB, II, DL, get(RISCV::SLLI), VL) in getVLENFactoredAmount()
1880 BuildMI(MBB, II, DL, get(RISCV::SLLI), VL) in getVLENFactoredAmount()
1891 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) in getVLENFactoredAmount()
1902 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) in getVLENFactoredAmount()
H A DRISCVInstrInfo.td639 def SLLI : Shift_ri<0b00000, 0b001, "slli">;
992 (SLLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1187 def : PatGprUimmLog2XLen<shl, SLLI>;
1193 (SLLI (SRLI $rs, LeadingOnesMask:$mask), LeadingOnesMask:$mask)>;
1195 (SRLI (SLLI $rs, TrailingOnesMask:$mask), TrailingOnesMask:$mask)>;
1572 def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (SRLI (SLLI GPR:$rs1, 32), 32)>;
1577 (SRLI (SLLI GPR:$rs1, 32), (ImmSubFrom32 uimm5:$shamt))>;
H A DRISCVInstrInfoZb.td1137 (SLLI (SH1ADD GPR:$r, GPR:$r),
1140 (SLLI (SH2ADD GPR:$r, GPR:$r),
1143 (SLLI (SH3ADD GPR:$r, GPR:$r),
H A DRISCVFrameLowering.cpp575 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg) in emitPrologue()
H A DRISCVInstrInfoC.td854 def : CompressPat<(SLLI GPRNoX0:$rs1, GPRNoX0:$rs1, uimmlog2xlennonzero:$imm),
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dpass-fast-math-flags-sdnode.ll15 ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 32
16 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gprnox0 = SRLI killed [[SLLI]], 32
H A Dget-vlen-debugloc.mir31 ; CHECK-NEXT: $x10 = frame-setup SLLI killed $x10, 1
36 ; CHECK-NEXT: $x10 = frame-destroy SLLI killed $x10, 1
H A Dzvlsseg-spill.mir27 ; CHECK-NEXT: $x12 = frame-setup SLLI killed $x12, 3
39 ; CHECK-NEXT: $x10 = frame-destroy SLLI killed $x10, 3
H A Daddi-scalable-offset.mir41 ; CHECK-NEXT: $x12 = frame-setup SLLI killed $x12, 1
46 ; CHECK-NEXT: $x11 = SLLI killed $x11, 1
H A Dwrong-stack-offset-for-rvv-object.mir158 ; CHECK-NEXT: $x10 = frame-setup SLLI killed $x10, 1
163 ; CHECK-NEXT: $x10 = SLLI killed $x10, 1
167 ; CHECK-NEXT: $x10 = SLLI killed $x10, 1
H A Demergency-slot.mir128 ; CHECK-NEXT: renamable $x13 = SLLI renamable $x11, 3
204 renamable $x13 = SLLI renamable $x11, 3
H A Dvmv-copy.mir200 ; CHECK-NEXT: $x12 = SLLI $x12, 1
206 $x12 = SLLI $x12, 1
/llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp24 case RISCV::SLLI: in getInstSeqCost()
150 Res.push_back(RISCVMatInt::Inst(RISCV::SLLI, ShiftAmount)); in generateInstSeqImpl()
188 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::SLLI, TrailingZeros)); in generateInstSeq()
412 case RISCV::SLLI: in getOpndKind()
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dand.ll9 ; with the remainder zero, we can replace it with SLLI + SLRI
75 ; with the remainder zero, we can replace it with SRLI + SLLI.
H A Dimm.ll225 ; This can be materialized with ADDI+SLLI, improving compressibility.
931 ; This constant can be materialized for RV64 with ADDI+SLLI+ADDI+ADDI.
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td441 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>;
H A DMipsScheduleGeneric.td1562 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp2471 emitToStreamer(Out, MCInstBuilder(RISCV::SLLI) in emitPseudoExtend()