| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVCodeGenPrepare.cpp | 75 auto *SExt = new SExtInst(Src, ZExt->getType(), "", ZExt); in optimizeZExt() local 76 SExt->takeName(ZExt); in optimizeZExt() 77 SExt->setDebugLoc(ZExt->getDebugLoc()); in optimizeZExt() 79 ZExt->replaceAllUsesWith(SExt); in optimizeZExt() 89 auto *SExt = new SExtInst(Src, ZExt->getType(), "", ZExt); in optimizeZExt() local 90 SExt->takeName(ZExt); in optimizeZExt() 91 SExt->setDebugLoc(ZExt->getDebugLoc()); in optimizeZExt() 93 ZExt->replaceAllUsesWith(SExt); in optimizeZExt()
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| /llvm-project-15.0.7/llvm/unittests/IR/ |
| H A D | AttributesTest.cpp | 29 AttributeList::get(C, 2, Attribute::SExt)}; in TEST() 54 AttributeList::get(C, 1, Attribute::SExt)}; in TEST() 70 B.addAttribute(Attribute::SExt); in TEST() 72 EXPECT_TRUE(AL.hasRetAttr(Attribute::SExt)); in TEST() 172 …nsigned, Attribute> Attrs[] = { { AttributeList::ReturnIndex, Attribute::get(C, Attribute::SExt) }, in TEST() 240 AL.addRetAttribute(C, Attribute::SExt).print(OS); in TEST()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | LowerExpectIntrinsic.cpp | 146 if (SExtInst *SExt = dyn_cast<SExtInst>(V)) { in handlePhiDef() local 147 V = SExt->getOperand(0); in handlePhiDef() 148 Operations.push_back(SExt); in handlePhiDef() 175 case Instruction::SExt: in handlePhiDef()
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| H A D | SpeculativeExecution.cpp | 228 case Instruction::SExt: in ComputeSpeculationCost()
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| H A D | NaryReassociate.cpp | 363 if (SExtInst *SExt = dyn_cast<SExtInst>(IndexToSplit)) { in tryReassociateGEPAtIndex() local 364 IndexToSplit = SExt->getOperand(0); in tryReassociateGEPAtIndex()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMParallelDSP.cpp | 104 if (auto *SExt = dyn_cast<SExtInst>(V)) { in InsertMuls() local 105 if (auto *I = dyn_cast<Instruction>(SExt->getOperand(0))) in InsertMuls() 328 if (auto *SExt = dyn_cast<SExtInst>(V)) { in IsNarrowSequence() local 329 if (SExt->getSrcTy()->getIntegerBitWidth() != MaxBitWidth) in IsNarrowSequence() 332 if (auto *Ld = dyn_cast<LoadInst>(SExt->getOperand(0))) { in IsNarrowSequence() 473 case Instruction::SExt: in Search()
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| H A D | MVELaneInterleavingPass.cpp | 186 case Instruction::SExt: in tryInterleave()
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| /llvm-project-15.0.7/llvm/include/llvm/Analysis/ |
| H A D | TargetLibraryInfo.h | 389 return Signed ? Attribute::SExt : Attribute::ZExt; 391 return Attribute::SExt; 400 return Signed ? Attribute::SExt : Attribute::ZExt;
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| /llvm-project-15.0.7/llvm/lib/Transforms/AggressiveInstCombine/ |
| H A D | TruncInstCombine.cpp | 53 case Instruction::SExt: in getRelevantOperands() 130 case Instruction::SExt: in buildTruncExpressionGraph() 396 case Instruction::SExt: { in ReduceExpressionGraph() 409 Opc == Instruction::SExt); in ReduceExpressionGraph()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | Analysis.cpp | 597 } else if (CallerAttrs.contains(Attribute::SExt)) { in attributesPermitTailCall() 598 if (!CalleeAttrs.contains(Attribute::SExt)) in attributesPermitTailCall() 602 CallerAttrs.removeAttribute(Attribute::SExt); in attributesPermitTailCall() 603 CalleeAttrs.removeAttribute(Attribute::SExt); in attributesPermitTailCall() 617 CalleeAttrs.removeAttribute(Attribute::SExt); in attributesPermitTailCall()
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| H A D | InterleavedLoadCombinePass.cpp | 169 SExt, enumerator 504 pushBOperation(SExt, APInt(sizeof(n) * 8, n)); in sextOrTrunc() 592 case SExt: in print()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitTracker.h | 62 enum { SExt, ZExt }; enumerator
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| H A D | HexagonOptimizeSZextends.cpp | 75 if (F.getAttributes().hasParamAttr(Idx, Attribute::SExt)) { in runOnFunction()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 842 if (Attrs.hasParamAttr(I, Attribute::SExt)) in selectCall() 1010 const auto *SExt = cast<SExtInst>(I); in selectSExt() local 1012 const Value *Op = SExt->getOperand(0); in selectSExt() 1014 MVT::SimpleValueType To = getLegalType(getSimpleType(SExt->getType())); in selectSExt() 1022 updateValueMap(SExt, Reg); in selectSExt() 1372 if (FuncInfo.Fn->getAttributes().hasRetAttr(Attribute::SExt)) in selectRet() 1406 case Instruction::SExt: in fastSelectInstruction()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | FastISel.h | 113 RetSExt = Call.hasRetAttr(Attribute::SExt); in setCallee() 137 RetSExt = Call.hasRetAttr(Attribute::SExt);
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| H A D | CallingConvLower.h | 35 SExt, // The value is sign extended in the location. enumerator 155 return (HTP == AExt || HTP == SExt || HTP == ZExt); in isExtInLoc()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86PartialReduction.cpp | 84 (Cast->getOpcode() == Instruction::SExt || in matchVPDPBUSDPattern() 151 (Cast->getOpcode() == Instruction::SExt || in tryMAddReplacement()
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| /llvm-project-15.0.7/llvm/lib/Target/DirectX/ |
| H A D | DXILPrepare.cpp | 67 Attribute::SExt, in isValidForDXIL()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTargetTransformInfo.cpp | 207 case Instruction::SExt: in getIntImmCostInst() 782 if ((Opcode == Instruction::ZExt || Opcode == Instruction::SExt) && in getCastInstrCost() 790 if (Opcode == Instruction::SExt) in getCastInstrCost() 819 if (Opcode == Instruction::ZExt || Opcode == Instruction::SExt) { in getCastInstrCost()
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineNegator.cpp | 208 case Instruction::SExt: in visitImpl() 212 return I->getOpcode() == Instruction::SExt in visitImpl()
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| /llvm-project-15.0.7/clang/include/clang/CodeGen/ |
| H A D | CGFunctionInfo.h | 332 void setSignExt(bool SExt) { in setSignExt() argument 334 SignExt = SExt; in setSignExt()
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| /llvm-project-15.0.7/llvm/lib/Target/BPF/ |
| H A D | BPFAdjustOpt.cpp | 352 Inst->getOpcode() == Instruction::SExt) { in avoidSpeculation()
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| /llvm-project-15.0.7/llvm/lib/IR/ |
| H A D | Instructions.cpp | 2884 case Instruction::SExt: in isIntegerCast() 2927 case Instruction::SExt: in isNoopCast() 3214 case SExt: return new SExtInst (S, Ty, Name, InsertAtEnd); in Create() 3250 return Create(Instruction::SExt, S, Ty, Name, InsertBefore); in CreateSExtOrBitCast() 3258 return Create(Instruction::SExt, S, Ty, Name, InsertAtEnd); in CreateSExtOrBitCast() 3361 (isSigned ? Instruction::SExt : Instruction::ZExt))); in CreateIntegerCast() 3375 (isSigned ? Instruction::SExt : Instruction::ZExt))); in CreateIntegerCast() 3498 return SExt; // signed -> SEXT in getCastOpcode() 3599 case Instruction::SExt: in castIsValid() 3694 ) : CastInst(Ty, SExt, S, Name, InsertBefore) { in SExtInst() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 859 case Instruction::SExt: in computeAddress() 3020 case CCValAssign::SExt: { in processCallArgs() 4601 } else if (const auto *SExt = dyn_cast<SExtInst>(Src0)) { in selectMul() local 4602 if (!isIntExtFree(SExt)) { in selectMul() 4604 if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), VT)) { in selectMul() 4607 Src0 = SExt->getOperand(0); in selectMul() 4665 } else if (const auto *SExt = dyn_cast<SExtInst>(Op0)) { in selectShift() local 4666 if (!isIntExtFree(SExt)) { in selectShift() 4668 if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), TmpVT)) { in selectShift() 4671 Op0 = SExt->getOperand(0); in selectShift() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURewriteOutArguments.cpp | 327 RetAttrs.addAttribute(Attribute::SExt); in runOnFunction()
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