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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3 |
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| #
59630917 |
| 02-Mar-2022 |
serge-sans-paille <[email protected]> |
Cleanup includes: Transform/Scalar
Estimated impact on preprocessor output line:
before: 1062981579
after: 1062494547
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cl
Cleanup includes: Transform/Scalar
Estimated impact on preprocessor output line:
before: 1062981579
after: 1062494547
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D120817
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Revision tags: llvmorg-14.0.0-rc2 |
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| #
904a00d1 |
| 25-Feb-2022 |
Anton Afanasyev <[email protected]> |
[AggressiveInstCombine] Fix `TruncInstCombine` (fix f84d732f)
Erase phi-nodes from `InstInfoMap` before erasing themselves
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Revision tags: llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4 |
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| #
0dd84013 |
| 15-Sep-2021 |
Anton Afanasyev <[email protected]> |
[AggressiveInstCombine] Add `phi` nodes support to `TruncInstCombine`
Expand `TruncInstCombine` to handle loops by adding `phi` nodes
to expression graph.
Reviewed by: RKSimon, lebedev.ri
(recommi
[AggressiveInstCombine] Add `phi` nodes support to `TruncInstCombine`
Expand `TruncInstCombine` to handle loops by adding `phi` nodes
to expression graph.
Reviewed by: RKSimon, lebedev.ri
(recommit of fixed f84d732f, reverted by 8ad6d5e after sanitizer breakage)
Differential Revision: https://reviews.llvm.org/D109817
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8ad6d5e4 |
| 23-Feb-2022 |
Anton Afanasyev <[email protected]> |
Revert "[AggressiveInstCombine] Add `phi` nodes support to `TruncInstCombine`"
This reverts commit f84d732f8c1737940afab71824134f41f37a048b.
Breakage of "sanitizer-x86_64-linux-fast"
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| #
f84d732f |
| 15-Sep-2021 |
Anton Afanasyev <[email protected]> |
[AggressiveInstCombine] Add `phi` nodes support to `TruncInstCombine`
Expand `TruncInstCombine` to handle loops by adding `phi` nodes
to expression graph.
Reviewed by: RKSimon, lebedev.ri
Differen
[AggressiveInstCombine] Add `phi` nodes support to `TruncInstCombine`
Expand `TruncInstCombine` to handle loops by adding `phi` nodes
to expression graph.
Reviewed by: RKSimon, lebedev.ri
Differential Revision: https://reviews.llvm.org/D109817
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| #
7787a8f1 |
| 14-Dec-2021 |
Kazu Hirata <[email protected]> |
[llvm] Use llvm::reverse (NFC)
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Revision tags: llvmorg-13.0.0-rc3 |
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6a5f49a1 |
| 05-Sep-2021 |
Anton Afanasyev <[email protected]> |
[AggressiveInstCombine] Add `{insert/extract}element` to `TruncInstCombine` DAG
Alive2 for `{insert/extract}element`: https://alive2.llvm.org/ce/z/hwy_E-
Actually, no one file of test suite is touc
[AggressiveInstCombine] Add `{insert/extract}element` to `TruncInstCombine` DAG
Alive2 for `{insert/extract}element`: https://alive2.llvm.org/ce/z/hwy_E-
Actually, no one file of test suite is touched by this change,
which means that is rare pattern not generated by frontend. But
it's worth being in place.
Differential Revision: https://reviews.llvm.org/D109236
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| #
54d8ebbb |
| 07-Sep-2021 |
Anton Afanasyev <[email protected]> |
[AggressiveInstCombine] Add `udiv` and `urem` instrs to TruncInstCombine DAG
Add `udiv` and `urem` instructions to the DAG post-dominated by `trunc`,
allowing TruncInstCombine to reduce bitwidth of
[AggressiveInstCombine] Add `udiv` and `urem` instrs to TruncInstCombine DAG
Add `udiv` and `urem` instructions to the DAG post-dominated by `trunc`,
allowing TruncInstCombine to reduce bitwidth of expressions containing these
instructions. It is sufficient to require that all truncated bits of both
operands are zeros: https://alive2.llvm.org/ce/z/yiithn
(`urem` case is identical).
Differential Revision: https://reviews.llvm.org/D109515
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| #
d1f9b216 |
| 05-Sep-2021 |
Anton Afanasyev <[email protected]> |
[AggressiveInstCombine] Add `AssumptionCache` to aggressive instcombine
Add support for @llvm.assume() to TruncInstCombine allowing
optimizations based on these intrinsics while computing known bits.
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| #
8c0a1940 |
| 05-Sep-2021 |
Anton Afanasyev <[email protected]> |
[AggresiveInstCombine] Add wrapper calls for `KnownBits` computing
Precommit before `AssumptionCache` adding: reviews.llvm.org/D109141
Differential Revision: https://reviews.llvm.org/D109288
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Revision tags: llvmorg-13.0.0-rc2 |
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| #
bed58763 |
| 19-Aug-2021 |
Anton Afanasyev <[email protected]> |
[AggressiveInstCombine] Add arithmetic shift right instr to `TruncInstCombine` DAG
Add `ashr` instruction to the DAG post-dominated by `trunc`, allowing
`TruncInstCombine` to reduce bitwidth of expr
[AggressiveInstCombine] Add arithmetic shift right instr to `TruncInstCombine` DAG
Add `ashr` instruction to the DAG post-dominated by `trunc`, allowing
`TruncInstCombine` to reduce bitwidth of expressions containing
these instructions.
We should be shifting by less than the target bitwidth.
Also it is sufficient to require that all truncated bits
of the value-to-be-shifted are sign bits (all zeros or ones) and
one sign bit is left untruncated: https://alive2.llvm.org/ce/z/Ajo2__
Part of https://reviews.llvm.org/D107766
Differential Revision: https://reviews.llvm.org/D108355
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| #
dd19f342 |
| 20-Aug-2021 |
Sanjay Patel <[email protected]> |
[AggressiveInstCombine] guard against applying instruction flags with constant folding
This is a minimized version of a crash reported in:
D108201
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| #
3890ce70 |
| 19-Aug-2021 |
Anton Afanasyev <[email protected]> |
[NFC][AggressiveInstCombine] Simplify code for shift truncation
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| #
cfb6dfcb |
| 17-Aug-2021 |
Anton Afanasyev <[email protected]> |
[AggressiveInstCombine] Add logical shift right instr to `TruncInstCombine` DAG
Add `lshr` instruction to the DAG post-dominated by `trunc`, allowing
TruncInstCombine to reduce bitwidth of expressio
[AggressiveInstCombine] Add logical shift right instr to `TruncInstCombine` DAG
Add `lshr` instruction to the DAG post-dominated by `trunc`, allowing
TruncInstCombine to reduce bitwidth of expressions containing
these instructions.
We should be shifting by less than the target bitwidth.
Also it is sufficient to require that all truncated bits
of the value-to-be-shifted are zeros: https://alive2.llvm.org/ce/z/_LytbB
Alive2 variable-length proof:
https://godbolt.org/z/1srE1aqzf => s/32/8/ => https://alive2.llvm.org/ce/z/StwPia
Part of https://reviews.llvm.org/D107766
Differential Revision: https://reviews.llvm.org/D108201
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| #
803270c0 |
| 18-Aug-2021 |
Anton Afanasyev <[email protected]> |
[AggressiveInstCombine] Fix unsigned overflow
Fix issue reported here: https://reviews.llvm.org/D108091#2950930
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| #
1f3e35b6 |
| 12-Aug-2021 |
Anton Afanasyev <[email protected]> |
[AggressiveInstCombine] Add shift left instruction to `TruncInstCombine` DAG
Add `shl` instruction to the DAG post-dominated by `trunc`, allowing
TruncInstCombine to reduce bitwidth of expressions c
[AggressiveInstCombine] Add shift left instruction to `TruncInstCombine` DAG
Add `shl` instruction to the DAG post-dominated by `trunc`, allowing
TruncInstCombine to reduce bitwidth of expressions containing left shifts.
The only thing we need to check is that the target bitwidth must be wider
than the maximal shift amount: https://alive2.llvm.org/ce/z/AwArqu
Part of https://reviews.llvm.org/D107766
Differential Revision: https://reviews.llvm.org/D108091
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Revision tags: llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2 |
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| #
e53472de |
| 21-Jan-2021 |
Kazu Hirata <[email protected]> |
[Transforms] Use llvm::append_range (NFC)
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Revision tags: llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2 |
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| #
137674f8 |
| 08-Dec-2020 |
Jun Ma <[email protected]> |
[TruncInstCombine] Remove scalable vector restriction
Differential Revision: https://reviews.llvm.org/D92819
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Revision tags: llvmorg-11.0.1-rc1, llvmorg-11.0.0, llvmorg-11.0.0-rc6 |
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| #
0347f3ea |
| 02-Oct-2020 |
Simon Pilgrim <[email protected]> |
TruncInstCombine.cpp - fix header include ordering to fix llvm-include-order clang-tidy warning. NFCI.
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| #
5e8e89d8 |
| 02-Oct-2020 |
Simon Pilgrim <[email protected]> |
TruncInstCombine.cpp - use auto * to fix llvm-qualified-auto clang-tidy warning. NFCI.
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Revision tags: llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2 |
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| #
416a6a85 |
| 14-Aug-2020 |
Christopher Tetreault <[email protected]> |
[SVE] Remove calls to VectorType::getNumElements from AggressiveInstCombine
Reviewed By: fpetrogalli
Differential Revision: https://reviews.llvm.org/D82218
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Revision tags: llvmorg-11.0.0-rc1, llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3, llvmorg-10.0.1-rc2 |
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| #
dd3580cc |
| 25-Jun-2020 |
Simon Pilgrim <[email protected]> |
AggressiveInstCombineInternal.h - reduce unnecessary includes to forward declarations. NFC.
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| #
e987ee63 |
| 13-Jun-2020 |
Roman Lebedev <[email protected]> |
[NFCI][AggressiveInstCombiner] Add `STATISTIC()`s for transforms
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| #
e6cf402e |
| 29-May-2020 |
Christopher Tetreault <[email protected]> |
[SVE] Eliminate calls to default-false VectorType::get() from AggressiveInstCombine
Reviewers: efriedma, aymanmus, c-rhodes, david-arm
Reviewed By: david-arm
Subscribers: tschuett, hiraditya, rkru
[SVE] Eliminate calls to default-false VectorType::get() from AggressiveInstCombine
Reviewers: efriedma, aymanmus, c-rhodes, david-arm
Reviewed By: david-arm
Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D80332
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Revision tags: llvmorg-10.0.1-rc1, llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5, llvmorg-10.0.0-rc4, llvmorg-10.0.0-rc3 |
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0e890cd4 |
| 03-Mar-2020 |
Nikita Popov <[email protected]> |
[ConstantFolding] Always return something from ConstantFoldConstant
Spin-off from D75407. As described there, ConstantFoldConstant()
currently returns null for non-ConstantExpr/ConstantVector inputs
[ConstantFolding] Always return something from ConstantFoldConstant
Spin-off from D75407. As described there, ConstantFoldConstant()
currently returns null for non-ConstantExpr/ConstantVector inputs,
but otherwise always returns non-null, independently of whether
any folding has happened or not.
This is confusing and makes consumer code more complicated.
I would expect either that ConstantFoldConstant() returns only if
it actually folded something, or that it always returns non-null.
I'm going to the latter possibility here, which appears to be more
useful considering existing usage.
Differential Revision: https://reviews.llvm.org/D75543
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