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Searched refs:SETNE (Results 1 – 25 of 60) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1449 SETNE, // 1 X 1 1 0 True if not equal enumerator
1470 return Code == SETEQ || Code == SETNE; in isIntEqualitySetCC()
/llvm-project-15.0.7/llvm/test/TableGen/
H A DGlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td62 …ct:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$cond, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (s…
99 def : Pat<(i32 (select (i32 (setcc GPR32:$cond, (i32 0), (OtherVT SETNE))),
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp34 case ISD::SETNE: in intCondCode2Icc()
65 case ISD::SETNE: in fpCondCode2Fcc()
H A DVECustomDAG.cpp448 return DAG.getSetCC(DL, BoolVecTy, BCVec, ZeroVec, ISD::CondCode::SETNE); in getMaskBroadcast()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAnalysis.cpp212 case ISD::SETONE: case ISD::SETUNE: return ISD::SETNE; in getFCmpCodeWithoutNaN()
224 case ICmpInst::ICMP_NE: return ISD::SETNE; in getICmpCondCode()
242 case ISD::SETNE: in getICmpCondCode()
H A DTargetLoweringBase.cpp674 CCs[RTLIB::UNE_F32] = ISD::SETNE; in InitCmpLibcallCCs()
675 CCs[RTLIB::UNE_F64] = ISD::SETNE; in InitCmpLibcallCCs()
676 CCs[RTLIB::UNE_F128] = ISD::SETNE; in InitCmpLibcallCCs()
677 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; in InitCmpLibcallCCs()
694 CCs[RTLIB::UO_F32] = ISD::SETNE; in InitCmpLibcallCCs()
695 CCs[RTLIB::UO_F64] = ISD::SETNE; in InitCmpLibcallCCs()
696 CCs[RTLIB::UO_F128] = ISD::SETNE; in InitCmpLibcallCCs()
697 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; in InitCmpLibcallCCs()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp322 case ISD::SETNE: in softenSetCCOperands()
3784 NewCond = ISD::CondCode::SETNE; in optimizeSetCCOfSignedTruncationCheck()
3788 NewCond = ISD::CondCode::SETNE; in optimizeSetCCOfSignedTruncationCheck()
4025 if (Cond != ISD::SETEQ && Cond != ISD::SETNE) in foldSetCCWithRotate()
4070 if (Cond != ISD::SETEQ && Cond != ISD::SETNE) in foldSetCCWithFunnelShift()
4196 Cond = ISD::SETNE; in SimplifySetCC()
4374 case ISD::SETNE: in SimplifySetCC()
4392 case ISD::SETNE: in SimplifySetCC()
4999 case ISD::SETNE: // X != Y --> (X^Y) in SimplifySetCC()
9314 LHS, ISD::SETNE); in expandMULO()
[all …]
H A DLegalizeIntegerTypes.cpp1117 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_SADDSUBO()
1433 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_UADDSUBO()
1532 ISD::SETNE); in PromoteIntRes_XMULO()
3882 SatMax = DAG.getSetCC(dl, BoolNVT, Tmp, NVTZero, ISD::SETNE); in ExpandIntRes_MULFIX()
4390 DAG.getSetCC(dl, BitVT, LHSHigh, HalfZero, ISD::SETNE), in ExpandIntRes_XMULO()
4391 DAG.getSetCC(dl, BitVT, RHSHigh, HalfZero, ISD::SETNE)); in ExpandIntRes_XMULO()
4493 ISD::SETNE); in ExpandIntRes_XMULO()
4648 Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ); in ExpandIntRes_FunnelShift()
4763 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { in IntegerExpandSetCCOperands()
4912 CCCode = ISD::SETNE; in ExpandIntOp_BR_CC()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h114 case ISD::SETNE: in getRISCVCCForIntCC()
H A DRISCVInstrInfoVSDPatterns.td688 defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSNE", SETNE>;
696 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSNE", SETNE, SETNE>;
706 defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSNE", SETNE>;
957 defm : VPatFPSetCCSDNode_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">;
H A DRISCVInstrInfoVVLPatterns.td1064 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSNE", SETNE>;
1072 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>;
1082 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>;
1290 defm : VPatFPSetCCVL_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3178 case ISD::SETNE: { in get32BitZExtCompare()
3355 case ISD::SETNE: { in get32BitSExtCompare()
3522 case ISD::SETNE: { in get64BitZExtCompare()
3681 case ISD::SETNE: { in get64BitSExtCompare()
4050 case ISD::SETNE: in SelectCC()
4077 case ISD::SETNE: in SelectCC()
4128 case ISD::SETNE: in getPredicateForSetCC()
4329 case ISD::SETNE: { in trySETCC()
4367 case ISD::SETNE: { in trySETCC()
4688 bool IsCCNE = CC == ISD::SETNE; in tryFoldSWTestBRCC()
[all …]
H A DPPCInstrInfo.td3379 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
3450 defm : ExtSetCCPat<SETNE,
3544 defm : ExtSetCCShiftPat<SETNE,
3654 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
3657 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3669 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3683 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3698 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3713 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
3785 defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETNE)),
[all …]
H A DPPCInstrP10.td1868 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
1879 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETNE)),
1881 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETNE)),
1896 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
1919 defm : P10ReverseSetBool<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
1926 defm : P10ReverseSetBool<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td344 defm : BRCond_Bin<SETNE, "FCMPNE", BT32, MVC32>;
402 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETNE)), bb:$imm16),
404 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETNE)),
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td326 def COND_ONE : PatFrags<(ops), [(OtherVT SETONE), (OtherVT SETNE)]>;
347 def COND_UNE_NE : PatFrags<(ops), [(OtherVT SETUNE), (OtherVT SETNE)]>;
363 def COND_NE : PatFrags<(ops), [(OtherVT SETNE), (OtherVT SETUNE)]>;
H A DAMDGPUISelLowering.cpp1310 case ISD::SETNE: in combineFMinMaxLegacy()
1844 SDValue Sel1 = DAG.getSelectCC(DL, C6, Zero, Add4, Add3, ISD::SETNE); in LowerUDIVREM64()
1845 SDValue Div = DAG.getSelectCC(DL, C3, Zero, Sel1, Mulhi3, ISD::SETNE); in LowerUDIVREM64()
1847 SDValue Sel2 = DAG.getSelectCC(DL, C6, Zero, Sub3, Sub2, ISD::SETNE); in LowerUDIVREM64()
1848 SDValue Rem = DAG.getSelectCC(DL, C3, Zero, Sel2, Sub1, ISD::SETNE); in LowerUDIVREM64()
2636 Zero, ISD::SETNE), DAG.getConstant(0x7c00, DL, MVT::i32)); in LowerFP_TO_FP16()
2655 SDValue D1 = DAG.getSelectCC(DL, D0, SigSetHigh, One, Zero, ISD::SETNE); in LowerFP_TO_FP16()
3511 if (CCOpcode == ISD::SETNE && in performCtlz_CttzCombine()
H A DR600ISelLowering.cpp899 case ISD::SETNE: in LowerSELECT_CC()
937 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
1846 case ISD::SETNE: return LHS; in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1507 case ISD::SETNE: in TranslateIntegerM68kCC()
1595 case ISD::SETNE: in TranslateM68kCC()
1927 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
1938 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
1944 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1); in LowerSETCC()
1957 if (Op0.getValueType() == MVT::i1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2175 if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) { in LowerSELECT()
2439 if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) { in LowerBRCOND()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td74 defm NE : ComparisonInt<SETNE, "ne ", 0x47, 0x52>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp2011 case ISD::SETNE: return ARMCC::NE; in IntCCToARMCC()
2048 case ISD::SETNE: in FPCCToARMCC()
5464 CC = ISD::SETNE; in LowerSELECT_CC()
5623 CC = ISD::SETNE; in OptimizeVFPBrcond()
5707 CC = ISD::SETNE; in LowerBR_CC()
6724 if (SetCCOpcode == ISD::SETNE) in LowerVSETCC()
6738 case ISD::SETNE: in LowerVSETCC()
6787 case ISD::SETNE: in LowerVSETCC()
10299 CC = ISD::SETNE; in LowerFSETCC()
17957 (CC == ISD::SETNE && Imm == 1) || in PerformHWLoopCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td1415 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1421 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1428 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1434 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h1241 X86_INTRINSIC_DATA(sse_comineq_ss, COMI, X86ISD::COMI, ISD::SETNE),
1258 X86_INTRINSIC_DATA(sse_ucomineq_ss, COMI, X86ISD::UCOMI, ISD::SETNE),
1266 X86_INTRINSIC_DATA(sse2_comineq_sd, COMI, X86ISD::COMI, ISD::SETNE),
1313 X86_INTRINSIC_DATA(sse2_ucomineq_sd, COMI, X86ISD::UCOMI, ISD::SETNE),
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp200 { RTLIB::UNE_F64, "__mspabi_cmpd", ISD::SETNE }, in MSP430TargetLowering()
206 { RTLIB::UNE_F32, "__mspabi_cmpf", ISD::SETNE }, in MSP430TargetLowering()
1058 case ISD::SETNE: in EmitCMP()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1463 case ISD::SETNE: return SPCC::ICC_NE; in IntCondCCodeToICC()
1482 case ISD::SETNE: in FPCondCCodeToFCC()
1995 CC == ISD::SETNE && in LookThroughSetCC()
3084 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); in LowerUMULO_SMULO()
3087 ISD::SETNE); in LowerUMULO_SMULO()

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